View LAN8700IC-AEZG_6247801.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

smsc lan8700/lan8700i revision 2.3 (04-12-11) datasheet datasheet product features lan8700/lan8700i 15kv esd protected mii/rmii 10/100 ethernet transceiver with hp auto-mdix support and flexpwr ? technology in a small footprint ? single-chip ethernet physical layer transceiver (phy) ? esd protection levels of 8kv hbm without external protection devices ? esd protection levels of en/iec61000-4-2, 8kv contact mode, and 15kv for air discharge mode per independent test facility ? comprehensive flexpwr ? technology ? flexible power management architecture ? lvcmos variable i/o voltage range: +1.6v to +3.6v ? integrated 3.3v to 1.8v regulator for optional single supply operation. ? regulator can be disabled if 1.8v system supply is available. ? performs hp auto-mdix in accordance with ieee 802.3ab specification ? cable length greater than 150 meters ? automatic polarity correction ? latch-up performance exceeds 150ma per eia/jesd 78, class ii ? energy detect power-down mode ? low current consumption power down mode ? low operating current consumption: ? 39ma typical in 10base-t and ? 79ma typical in 100base-tx mode ? supports auto-negotiation and parallel detection ? supports the media independent interface (mii) and reduced media independent interface (rmii) ? compliant with ieee 802.3-2005 standards ? mii pins tolerant to 3.6v ? ieee 802.3-2005 co mpliant register functions ? integrated dsp with adaptive equalizer ? baseline wander (blw) correction ? vendor specific register functions ? low profile 36-pin qfn lead-free rohs compliant package (6 x 6 x 0.9mm height) ? 4 led status indicators ? commercial operating temperature 0 c to 70 c ? industrial operating temperature -40 c to 85 c version available (lan8700i) applications ? set top boxes ? network printers and servers ? lan on motherboard ? 10/100 pcmcia/cardbus applications ? embedded telecom applications ? video record/playback systems ? cable modems/routers ? dsl modems/routers ? digital video recorders ? personal video recorders ? ip and video phones ? wireless access points ? digital televisions ? digital media adaptors/servers ? pos terminals ? automotive networking ? gaming consoles ? security systems ? poe applications ? access control
order numbers: lan8700c-aezg for 36-pin, qfn lead-free rohs compliant package LAN8700IC-AEZG for (industr ial temp) 36-pin, qfn lead-fr ee rohs compliant package 4900 pcs per tray lan8700c-aezg-tr for 36-pin, qfn lead-fr ee rohs compliant package (tape and reel) 3000 pcs per reel this product meets the halogen maximum concentration values per iec61249-2-21 for rohs compliance and environmen tal information, please visit www.smsc.com/rohs 15kv esd protected mii/rmii 10/100 ethernet transceiver with hp auto-mdix support and flexpwr ? technology in a small footprint datasheet revision 2.3 (04-12-11) 2 smsc lan8700/lan8700i datasheet 80 arkay drive, hauppauge, ny 11788 (631) 435-6000 or 1 (800) 443-semi copyright ? 2011 smsc or its subsidiaries. all rights reserved. circuit diagrams and other information relating to smsc produc ts are included as a means of illustrating typical applications. consequently, complete information sufficient for construction purposes is not necessarily given. although the information has been checked and is believed to be accurate, no re sponsibility is assumed for inaccuracies. smsc reserves the right to make changes to specifications and produc t descriptions at any time without notice. contact your local sm sc sales office to obtain the latest specifications before placing your product order. the provision of this inform ation does not convey to the purchaser of the described semicond uctor devices any licenses under any patent rights or other intellectual property rights of smsc or others. all sales are expressly conditional on your agreement to the te rms and conditions of the most recently dated version of smsc's standard terms of sale agreement dated before the date of your order (the "terms of sale agreement"). the pro duct may contain design defects or errors known as anomalies which may cause the product's functions to deviate from published specifications. anomaly sheets are availab le upon request. smsc products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property damage. any and all such uses without prior written approval of an officer of smsc and further testing and/or modification will be fully at the risk of the customer. copies of this document or other smsc literature, as well as the terms of sale agreement, may be obtained by visiting smsc?s website at h ttp://www.smsc.com. smsc is a registered trademark of standard microsystems corporation (?smsc?). product names and company names are the trademarks of their respective holders. smsc disclaims and excludes any and all warrant ies, including without limi tation any and all implied warranties of merchantabil ity, fitness for a particular purpose, title, a nd against infringement and the like, and any and all warranties arising from any cou rse of dealing or usage of trade. in no event shall smsc be liable for any direct, incidental, indi rect, special, punitive, or cons equential damages; or for lost data, profits, savings or revenues of any kind; regardless of the form of action, whether based on contrac t; tort; negligence of smsc or others; strict liability; breach of wa rranty; or otherwise; whether or not any remedy of buyer is h eld to have failed of its essential purpose, and whether or not smsc has been advised of the possibility of such damages.
15kv esd protected mii/rmii 10/100 ethernet transceiver with hp auto-mdix support and flexpwr ? technology in a small footprint datasheet smsc lan8700/lan8700i 3 revision 2.3 (04-12-11) datasheet table of contents chapter 1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.1 architectural overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 chapter 2 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.1 package pin-out diagram and signal table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 chapter 3 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.1 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 chapter 4 architecture details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.1 top level functional architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.2 100base-tx transmit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.2.1 100m transmit data across the mii/rmii interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.2.2 4b/5b encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.2.3 scrambling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.2.4 nrzi and mlt3 encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.2.5 100m transmit driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.2.6 100m phase lock loop (pll) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.3 100base-tx receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.3.1 100m receive input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.3.2 equalizer, baseline wander correction and clock and data recovery . . . . . . . . . . . . . 22 4.3.3 nrzi and mlt-3 decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.3.4 descrambling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.3.5 alignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.3.6 5b/4b decoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.3.7 receive data valid signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3 4.3.8 receiver errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.3.9 100m receive data across the mii/ rmii interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.4 10base-t transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.4.1 10m transmit data across the mii/rmii interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.4.2 manchester encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.4.3 10m transmit drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.5 10base-t receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.5.1 10m receive input and squelch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.5.2 manchester decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.5.3 10m receive data across the mii/rmii interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.5.4 jabber detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.6 mac interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.6.1 mii . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.6.2 rmii . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.6.3 mii vs. rmii configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.7 auto-negotiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.7.1 parallel detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.7.2 re-starting auto-negotiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 0 4.7.3 disabling auto-negotiation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.7.4 half vs. full duplex . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.8 hp auto-mdix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.9 internal +1.8v regulator disa ble . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.9.1 disable the internal +1.8v regulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.9.2 enable the internal +1.8v regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
15kv esd protected mii/rmii 10/100 ethernet transceiver with hp auto-mdix support and flexpwr ? technology in a small footprint datasheet revision 2.3 (04-12-11) 4 smsc lan8700/lan8700i datasheet 4.10 nint/tx_er/txd4 strapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.11 phy address strapping and led output polarity selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.12 variable voltage i/o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.12.1 boot strapping configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.12.2 i/o voltage stability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.13 phy management control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.13.1 serial management interface (smi). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 chapter 5 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.1 smi register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 5.2 smi register format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 5.3 interrupt management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 5.3.1 primary interrupt system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 5.3.2 alternate interrupt system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 5.4 miscellaneous functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 5.4.1 carrier sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 5.4.2 collision detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 5.4.3 isolate mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 5.4.4 link integrity test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 5.4.5 power-down modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 5.4.6 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 5.4.7 led description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 5.4.8 loopback operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 5.4.9 configuration signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 chapter 6 ac electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 6.1 serial management interface (smi) timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 6.2 mii 10/100base-tx/rx timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 6.2.1 mii 100base-t tx/rx timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 6.2.2 mii 10base-t tx/rx timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 6.3 rmii 10/100base-tx/rx timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 6.3.1 rmii 100base-t tx/rx timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 6.3.2 rmii 10base-t tx/rx timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 6.4 rmii clkin timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 6.5 reset timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 6.6 clock circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 chapter 7 dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 7.1 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 7.1.1 maximum guaranteed ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 7.1.2 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 7.1.3 power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 7.1.4 dc characteristics - input and output buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 chapter 8 application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 8.1 application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 8.2 magnetics selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 8.3 application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 8.4 reference designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 8.5 evaluation board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 chapter 9 package outline, tape and reel. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 chapter 10 datasheet revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
15kv esd protected mii/rmii 10/100 ethernet transceiver with hp auto-mdix support and flexpwr ? technology in a small footprint datasheet smsc lan8700/lan8700i 5 revision 2.3 (04-12-11) datasheet list of figures figure 1.1 lan8700/lan8700i system block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 1.2 lan8700/lan8700i architectural overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 2.1 package pinout (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 4.1 100base-tx data path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 4.2 receive data path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 4.3 relationship between received data and specific mii signals . . . . . . . . . . . . . . . . . . . . . . 24 figure 4.4 direct cable connection vs. cross-over cable connection. . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 4.5 phy address strapping on led?s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 4.6 mdio timing and frame structure - read cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 4.7 mdio timing and frame structure - write cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 5.1 reset timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 5.2 near-end loopback block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 5.3 far loopback block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 5.4 connector loopback block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 6.1 smi timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 figure 6.2 100m mii receive timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 6.3 100m mii transmit timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 figure 6.4 10m mii receive timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 figure 6.5 10m mii transmit timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 figure 6.6 100m rmii receive timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 figure 6.7 100m rmii transmit timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 figure 6.8 10m rmii receive timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 figure 6.9 10m rmii transmit timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 figure 6.10 reset timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 figure 8.1 simplified app lication diagram (see section 8.4, "reference designs" ) . . . . . . . . . . . . . . . . 75 figure 9.1 36-pin qfn package outline, 6 x 6 x 0.90 mm body (lead-free) . . . . . . . . . . . . . . . . . . . . 78 figure 9.2 qfn, 6x6 tape & reel. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 figure 9.3 reel dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
15kv esd protected mii/rmii 10/100 ethernet transceiver with hp auto-mdix support and flexpwr ? technology in a small footprint datasheet revision 2.3 (04-12-11) 6 smsc lan8700/lan8700i datasheet list of tables table 2.1 lan8700/lan8700i 36-pin qfn pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 3.1 mii signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 3.2 led signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 3.3 management signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 3.4 boot strap configuration inputs ( note 3.1 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 3.5 general signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 3.6 10/100 line interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 3.7 analog references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 3.8 power signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 4.1 4b/5b code table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 4.2 mii/rmii signal mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 4.3 boot strapping configuration resistors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 5.1 control register: register 0 (basic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 5.2 status register: register 1 (basic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 5.3 phy id 1 register: register 2 (extended) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 5.4 phy id 2 register: register 3 (extended) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 5.5 auto-negotiation advertisement: register 4 (extended) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 5.6 auto-negotiation link partner base page ability register: register 5 (extended) . . . . . . . . . 36 table 5.7 auto-negotiation expansion register: register 6 (e xtended). . . . . . . . . . . . . . . . . . . . . . . . . 36 table 5.8 auto-negotiation link partner next page tran smit register: register 7 (extended) . . . . . . . 36 table 5.9 register 8 (extended) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 5.10 register 9 (extended) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 5.11 register 10 (extended) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 5.12 register 11 (extended) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 5.13 register 12 (extended) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 5.14 register 13 (extended) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 5.15 register 14 (extended) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 5.16 register 15 (extended) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 5.17 silicon revision register 16: vendor-specific. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 5.18 mode control/ status register 17: vendor-specific . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 5.19 special modes register 18: vendor-specific . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 8 table 5.20 reserved register 19: vendor-specific. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 5.21 register 24: vendor-specific . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 5.22 register 25: vendor-specific . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 5.23 symbol error counter register 26: vendor-specific . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 5.24 special control/status indicati ons register 27: vendor-specific . . . . . . . . . . . . . . . . . . . . . . 39 table 5.25 special internal test ability control register 28: vendor-specific . . . . . . . . . . . . . . . . . . . . . . 39 table 5.26 interrupt source flags register 29: vendor-specific . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 5.27 interrupt mask register 30: vendor-specific . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 5.28 phy special control/status register 31: vendor-specific . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 5.29 smi register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 5.30 register 0 - basic control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 5.31 register 1 - basic status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 5.32 register 2 - phy identifier 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 5.33 register 3 - phy identifier 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 5.34 register 4 - auto negotiation adve rtisement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 5.35 register 5 - auto negotiation link partner ability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 5.36 register 6 - auto negotiation expansion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 5.37 register 16 - silicon revision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 5.38 register 17 - mode control/status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 5.39 register 18 - special modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 5.40 register 26 - symbol error counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
15kv esd protected mii/rmii 10/100 ethernet transceiver with hp auto-mdix support and flexpwr ? technology in a small footprint datasheet smsc lan8700/lan8700i 7 revision 2.3 (04-12-11) datasheet table 5.41 register 27 - special control/status indications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 5.42 register 28 - special internal te stability controls. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 5.43 register 29 - in terrupt source flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 5.44 register 30 - in terrupt mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 5.45 register 31 - phy special control/status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 5.46 interrupt management table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 5.47 alternative interrupt system management table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 5.48 mode[2:0] bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 6.1 smi timing values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 6.2 100m mii receive timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 6.3 100m mii transmit timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 6.4 10m mii receive timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 6.5 10m mii transmit timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 6.6 100m rmii receive timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 6.7 100m rmii transmit timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 6.8 10m rmii receive timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 6.9 10m rmii transmit timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 6.10 rmii clkin (ref_clk)timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6 table 6.11 reset timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 6.12 lan8700/lan8700i crystal specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 7.1 maximum conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 7.2 esd and latch-up performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 7.3 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 7.4 power consumption device only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 7.5 mii bus interface signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 7.6 lan interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 7.7 led signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 7.8 configuration inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 7.9 general signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 table 7.10 analog references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 table 7.11 internal pull-up / pull-down config urations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 table 7.12 100base-tx transceiver characterist ics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 7.13 10base-t transceiver char acteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 9.1 36-pin qfn package parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 table 10.1 customer revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
15kv esd protected mii/rmii 10/100 ethernet transceiver with hp auto-mdix support and flexpwr ? technology in a small footprint datasheet revision 2.3 (04-12-11) 8 smsc lan8700/lan8700i datasheet chapter 1 general description the smsc lan8700/lan8700i is a low-power, industrial temperature (lan8700i), variable i/o voltage, analog interface ic with hp auto-mdix support fo r high-performance embedded ethernet applications. the lan8700/lan8700i can be configured to operate on a single 3.3v supply utilizing an integrated 3.3v to 1.8v linear regulator. an option is availabl e to disable the linear regulator to optimize system designs that have a 1.8v power plane available. 1.1 architectural overview the lan8700/lan8700i consists of an encoder/dec oder, scrambler/descrambler, wave-shaping transmitter, output driver, twisted-pair receiver with adaptive equalizer and baseline wander (blw) correction, and clock and data recovery functi ons. the lan8700/lan8700i can be configured to support either the media independent interface (m ii) or the reduced media independent interface (rmii). the lan8700/lan8700i is compliant with ieee 802.3-2005 standards (mii pins tolerant to 3.6v) and supports both ieee 802.3-2005 compliant and vendor-specif ic register functions . it contains a full- duplex 10-base-t/100base-tx transceiver and supports 10-mbps (10base-t) operation on category 3 and category 5 unshie lded twisted-pair cable, and 100-mbps (100base-tx) operation on category 5 unshielded twisted-pair cable. hubs and switches with multiple integrated macs and external ph ys can have a large pin count due to the high number of pins needed fo r each mii interface. an increa sing pin count causes increasing cost. the rmii interface is intended for use on switch based asics or other embedded solutions requiring minimal pincount for ethernet connectivity. rmii requires only 6 pins for each mac to phy interface plus one common reference clock. the mii requi res 16 pins for each ma c to phy interface. the smsc lan8700/lan8700i is capable of running in rmii mode. please contact your smsc sales representative for the latest rmii specification. the lan8700/lan8700i referenced throughout this document applies to both the commercial temperature and industrial temperature component s. the lan8700i refers to only the industrial temperature component. figure 1.1 lan8700/lan8700i system block diagram 10/100 media access controller (mac) or soc smsc lan8700/ lan8700i magnetics ethernet system bus leds/gpio 25 mhz (mii) or 50mhz (rmiii) crystal or external clock mii /rmii
15kv esd protected mii/rmii 10/100 ethernet transceiver with hp auto-mdix support and flexpwr ? technology in a small footprint datasheet smsc lan8700/lan8700i 9 revision 2.3 (04-12-11) datasheet figure 1.2 lan8700/lan8700i architectural overview 10m rx logic 100m rx logic dsp system: clock data recovery equalizer analog-to- digital 100m pll squelch & filters 10m pll receive section central bias hp auto-mdix management control smi rmii / mii logic txp / txn txd[0..3] tx_en tx_er tx_clk rxd[0..3] rx_dv rx_er rx_clk crs col/crs_dv mdc mdio speed100 link activity fduplex led circuitry mode control nint nrst rxp / rxn 10m tx logic 10m transmitter 100m tx logic 100m transmitter transmit section pll xtal1 xtal2 mode0 mode1 mode2 phy address latches phyad[0..4] auto- negotiation interrupt generator mii mdix control
15kv esd protected mii/rmii 10/100 ethernet transceiver with hp auto-mdix support and flexpwr ? technology in a small footprint datasheet revision 2.3 (04-12-11) 10 smsc lan8700/lan8700i datasheet chapter 2 pin configuration 2.1 package pin-out di agram and signal table figure 2.1 package pinout (top view) nint/tx_er/txd4 mdc crs/phyad4 mdio nrst tx_en vdd_core vdd33 link/phyad1 activity/phyad2 fduplex/phyad3 xtal2 clkin /xtal1 rxd3/nintsel rxd1/mode1 rxd2/mode2 txd3 rx_clk/regoff tx_clk rx_er/rxd4 vddio txd1 txd0 txd2 col/rmii/crs_dv txp rxn vdda3.3 exres1 vdda3.3 rxp vdda3.3 1 2 3 4 5 6 7 8 lan8700/lan8700i mii/rmii ethernet phy 36 pin qfn gnd flag 10 11 12 13 14 15 16 24 23 22 21 20 19 32 31 30 29 28 speed100/phyad0 9rx_dv rxd0/mode0 17 txn 18 27 26 25 36 35 34 33
15kv esd protected mii/rmii 10/100 ethernet transceiver with hp auto-mdix support and flexpwr ? technology in a small footprint datasheet smsc lan8700/lan8700i 11 revision 2.3 (04-12-11) datasheet table 2.1 lan8700/lan8700i 36-pin qfn pinout pin no. pin name pin no. pin name 1 nint/tx_er/txd4 19 rx_dv 2 mdc 20 rx_clk/regoff 3 crs/phyad4 21 rx_er/rxd4 4mdio22 txclk 5nrst23 txd0 6 tx_en 24 txd1 7 vdd33 25 vddio 8vdd_core26 txd2 9 speed100/phyad0 27 txd3 10 link/phyad1 28 txn 11 activity/phyad2 29 txp 12 fduplex/phyad3 30 vdda3.3 13 xtal2 31 rxn 14 clkin/xtal1 32 rxp 15 rxd3/nintsel 33 vdda3.3 16 rxd2/mode2 34 exres1 17 rxd1/mode1 35 vdda3.3 18 rxd0/mode0 36 col/rmii/crs_dv
15kv esd protected mii/rmii 10/100 ethernet transceiver with hp auto-mdix support and flexpwr ? technology in a small footprint datasheet revision 2.3 (04-12-11) 12 smsc lan8700/lan8700i datasheet chapter 3 pin description this chapter describes the signals on each pin. when a lower case ?n? is used at the beginning of the signal name, it indicates that the signal is active lo w. for example, nrst indicates that the reset signal is active low. 3.1 i/o signals the following buffer types are shown in the type column of the tables in this chapter. ? i input. digital lvcmos levels. ? ipd input with internal pull-down. digital lvcmos levels. ? o output. digital lvcmos levels. ? opd output with internal pull-down. digital lvcmos levels. ? i/o input or output . digital lvcmos levels. ? iopd input or output with internal pull-down. digital lvcmos levels. ? iopu input or output with internal pull-up. digital lvcmos levels. note: the digital signals are not 5v tolerant.they are variable voltage from +1.6v to +3.6v. ? ai input. analog levels.. ? ao output. analog levels. table 3.1 mii signals signal name type description txd0 i transmit data 0 : bit 0 of the 4 data bits that are accepted by the phy for transmission. txd1 i transmit data 1 : bit 1 of the 4 data bits that are accepted by the phy for transmission. txd2 i transmit data 2 : bit 2 of the 4 data bits that are accepted by the phy for transmission note: this signal should be grounded in rmii mode. txd3 i transmit data 3 : bit 3 of the 4 data bits that are accepted by the phy for transmission. note: this signal should be grounded in rmii mode nint/ tx_er/ txd4 iopu mii transmit error : when driven high, the 4b/5b encode process substitutes the transmit error code-group (/h/) for the encoded data word. this input is ignored in 10base-t operation. mii transmit data 4: in symbol interface (5b decoding) mode, this signal becomes the mii transmit data 4 line, the msb of the 5-bit symbol code-group. notes: ? this signal is not used in rmii mode. ? this signal is mux?d with nint ? see section 4.10, "nint/tx_er/txd4 strapping," on page 32 for additional information on configuration/st rapping options. tx_en ipd transmit enable : indicates that valid data is presented on the txd[3:0] signals, for transmission . in rmii mode, only txd[1:0] have valid data.
15kv esd protected mii/rmii 10/100 ethernet transceiver with hp auto-mdix support and flexpwr ? technology in a small footprint datasheet smsc lan8700/lan8700i 13 revision 2.3 (04-12-11) datasheet tx_clk o transmit clock : 25mhz in 100base-tx mode. 2.5mhz in 10base-t mode. note: this signal is not used in rmii mode. note: for proper txclk operation, rx_er and rx_dv must not be driven high externally on a hardware reset or on a lan8700 power up. rxd0/ mode0 iopu receive data 0 : bit 0 of the 4 data bits that are sent by the phy in the receive path. phy operating mode bit 0: set the default mode of the phy. note: see section 5.4.9.2, "mode bus ? mode[2:0]," on page 56 , for the mode options rxd1/ mode1 iopu receive data 1 : bit 1 of the 4 data bits that are sent by the phy in the receive path. phy operating mode bit 1: set the default mode of the phy. note: see section 5.4.9.2, "mode bus ? mode[2:0]," on page 56 , for the mode options. rxd2/ mode2 iopu receive data 2 : bit 2 of the 4 data bits that are sent by the phy in the receive path. phy operating mode bit 2: set the default mode of the phy. notes: ? rxd2 is not used in rmii mode. ? see section 5.4.9.2, "mode bu s ? mode[2:0]," on page 56 , for the mode options. rxd3/ nintsel iopu receive data 3 : bit 3 of the 4 data bits that are sent by the phy in the receive path. nintsel : on power-up or external reset, the mode of the nint/txer/txd4 pin is selected. ? when rxd3/nintsel is floated or pulled to vddio, nint is selected for operation on pin nint/txer/txd4 (default). ? when rxd3/nintsel is pulled lo w to vss through a resistor, (see table 4.3, ?boot strapping configuration resistors,? on page 33 ), txer/txd4 is selected for operation on pin nint/txer/txd4. notes: ? rxd3 is not used in rmii mode ? if the nint/txer/txd4 pin is co nfigured for nint mode, then a pull-up resistor is needed to vddio on the nint/txer/txd4 pin. see table 4.3, ?boot strapping configuration resistors,? on page 33 . ? see section 4.10, "nint/tx_er/txd4 strapping," on page 32 for additional information on configuration/st rapping options. table 3.1 mii signals (continued) signal name type description
15kv esd protected mii/rmii 10/100 ethernet transceiver with hp auto-mdix support and flexpwr ? technology in a small footprint datasheet revision 2.3 (04-12-11) 14 smsc lan8700/lan8700i datasheet rx_er/ rxd4/ opd receive error : asserted to indicate that an error was detected somewhere in the frame presently being transferred from the phy. mii receive data 4 : in symbol interface (5b decoding) mode, this signal is the mii receive data 4 signal, the msb of the received 5-bit symbol code-group. unless configured in this mode, the pin functions as rx_er. note: this pin has an internal pull-down resistor, and must not be high during reset. the rx_er signal is optional in rmii mode. rx_dv o receive data valid : indicates that recovered and decoded data nibbles are being presented on rxd[3:0]. note: this pin has an internal pull-down resistor, and must not be high during reset. this signal is not used in rmii mode. rx_clk/ regoff iopd receive clock : in mii mode, this pin is the receive clock output. 25mhz in 100base-tx mode. 2.5mhz in 10base-t mode. note: this signal is not used in rmii mode. regulator off : this pin pulled up to configure the internal 1.8v regulator off. as described in section 4.9 , this pin is sampled during the power-on sequence to determine if the internal regulator should turn on. when the regulator is disabled, external 1.8v must be supplied to vdd_co re, and the voltage at vdd33 must be at least 2.64v before voltage is applied to vdd_core. col/ rmii/ crs_dv iopd mii mode collision detect : asserted to indicate detection of collision condition. rmii ? mii/rmii mode selection is latched on the rising edge of the internal reset (nreset) based on the following strapping: ? float this pin for mii mode or pull-high with an external resistor to vddio (see table 4.3, ?boot strapping configuration resistors,? on page 33 ) to set the device in rmii mode. ? see section 4.6.3, "mii vs. rm ii configuration," on page 28 for more details. rmii mode crs_dv (carrier sense/receive data valid) asserted to indicate when the receive medium is non-idle. when a 10bt packet is received, crs_dv is asserted, but rxd[1:0] is held low until the sfd byte (10101011) is received. in 10bt, half- duplex mode, transmitted data is not looped back onto the receive data pins, per the rmii standard. crs/ phyad4 iopu carrier sense : indicates detection of carrier. note: this signal is mux?d with phyad4 table 3.1 mii signals (continued) signal name type description
15kv esd protected mii/rmii 10/100 ethernet transceiver with hp auto-mdix support and flexpwr ? technology in a small footprint datasheet smsc lan8700/lan8700i 15 revision 2.3 (04-12-11) datasheet table 3.2 led signals signal name type description speed100/ phyad0 iopu led1 ? speed100 indication. active i ndicates that the selected speed is 100mbps. inactive indicates that the selected speed is 10mbps. note: this signal is mux?d with phyad0 link/ phyad1 iopu led2 ? link on indication. active indicates that the link (100base-tx or 10base-t) is on. note: this signal is mux?d with phyad1 activity/ phyad2 iopu led3 ? activity indication. active indicates that there is carrier sense (crs) from the active pmd. note: this signal is mux?d with phyad2 fduplex/ phyad3 iopu led4 ? duplex indication. active indicates that the phy is in full-duplex mode. note: this signal is mux?d with phyad3 table 3.3 management signals signal name type description mdio iopd management data input/output : serial management data input/output. mdc ipd management clock : serial management clock. table 3.4 boot strap configuration inputs ( note 3.1 ) signal name type description crs/ phyad4 iopu phy address bit 4: set the default address of the phy. this signal is mux?d with crs note: this signal is mux?d with crs fduplex/ phyad3 iopu phy address bit 3: set the default address of the phy. note: this signal is mux?d with fduplex activity/ phyad2 iopu phy address bit 2: set the default address of the phy. note: this signal is mux?d with activity link/ phyad1 iopu phy address bit 1: set the default address of the phy. note: this signal is mux?d with link speed100/ phyad0 iopu phy address bit 0: set the default address of the phy. note: this signal is mux?d with speed100 rxd2/ mode2 iopu phy operating mode bit 2: set the default mode of the phy. see section 5.4.9.2, "mode bu s ? mode[2:0]," on page 56 , for the mode options. note: this signal is mux?d with rxd2
15kv esd protected mii/rmii 10/100 ethernet transceiver with hp auto-mdix support and flexpwr ? technology in a small footprint datasheet revision 2.3 (04-12-11) 16 smsc lan8700/lan8700i datasheet note 3.1 on nrst transition high, the phy latches the st ate of the configuration pins in this table. rxd1/ mode1 iopu phy operating mode bit 1: set the default mode of the phy. see section 5.4.9.2, "mode bu s ? mode[2:0]," on page 56 , for the mode options. note: this signal is mux?d with rxd1 rxd0/ mode0 iopu phy operating mode bit 0: set the default mode of the phy. see section 5.4.9.2, "mode bu s ? mode[2:0]," on page 56 , for the mode options. note: this signal is mux?d with rxd0 col/ rmii/ crs_dv iopd digital communication mode: set the digital communications mode of the phy to rmii or mii. this signal is muxed with the collision signal (mii mode) and carrier sense/ receive data valid (rmii mode) ? float for mii mode. ? pull up with a resistor to vddio for rmii mode (see table 4.3, ?boot strapping configuration resistors,? on page 33 ) . rxd3/ nintsel iopu nint pin mode select: set the mode of pin 1. ? default, left floating pin 1 is nint, active low interrupt output. notes: for nint mode, tie nint/txd4/txer to vddio with a resistor (see table 4.3, ?boot strapping configuration resistors,? on page 33 ). ? pulled to vss by a resistor, (see table 4.3, ?boot strapping configuration resistors,? on page 33 ) pin 1 is tx_er/txd4, transmit error or transmit data 4 (5b mode). notes: for txd4/txer mode, do not tie nint/txd4/txer to vddio or ground. table 3.5 general signals signal name type description nint/ tx_er/ txd4 iopu lan interrupt ? active low output. place an external resistor (see table 4.3, ?boot strapping configuration resistors,? on page 33 ) pull-up to vcc 3.3v. notes: ? this signal is mux?d with txer/txd4 ? see section 4.10, "nint/tx_er/txd4 strapping," on page 32 for additional details on strapping options. nrst i external reset ? input of the system rese t. this signal is active low. when this pin is deasserted, the mode register bits are loaded from the mode pins as described in section 5.4.9.2 . table 3.4 boot strap configuration inputs ( note 3.1 ) (continued) signal name type description
15kv esd protected mii/rmii 10/100 ethernet transceiver with hp auto-mdix support and flexpwr ? technology in a small footprint datasheet smsc lan8700/lan8700i 17 revision 2.3 (04-12-11) datasheet clkin/ xtal1 i/o clock input ? 25 mhz or 50 mhz external clock or crystal input. in mii mode, this signal is the 25 mhz reference input clock in rmii mode, this signal is the 50 mhz reference input clock which is typically also driven to the rmii compliant ethernet mac clock input. note: see section 4.10, "nint/tx_er/txd4 strapping," on page 32 for additional details on strapping options. xtal2 o clock output ? 25 mhz crystal output. note: float this pin if using an external clock being driven through clkin/xtal1 table 3.6 10/100 line interface signal name type description txp ao transmit data positive : 100base-tx or 10base-t differential transmit outputs to magnetics. txn ao transmit data negative : 100base-tx or 10base-t differential transmit outputs to magnetics. rxp ai receive data positive : 100base-tx or 10base-t differential receive inputs from magnetics. rxn ai receive data negative : 100base-tx or 10base-t differential receive inputs from magnetics. table 3.7 analog references signal name type description exres1 ai connects to reference resistor of value 12.4k-ohm, 1% connected as described in the analog layout guidelines. the nominal voltage is 1.2v and ther efore the resistor will dissipate approximately 1mw of power. table 3.8 power signals signal name type description vddio power +1.6v to +3.6v vari able i/o pad power vdd33 power +3.3v core regulator input. vdda3.3 power +3.3v analog power table 3.5 general signals (continued) signal name type description
15kv esd protected mii/rmii 10/100 ethernet transceiver with hp auto-mdix support and flexpwr ? technology in a small footprint datasheet revision 2.3 (04-12-11) 18 smsc lan8700/lan8700i datasheet vdd_core power +1.8v (core voltage) - 1.8v for digital circuitry on chip. supplied by the on-chip regulator unless configured for regulator off mode using the rx_clk/regoff pin. place a 0.1uf capacitor near this pin and connect the capacitor from this pin to ground. when using the on-chip regulator, place a 4.7uf 20% capacitor with esr < 1ohm near this pin and connect the capacitor from this pin to ground. x5r or x7r ceramic capacitors are recommended since they exhibit an esr lower than 0.1ohm at frequencies greater than 10khz. vss power exposed ground flag. the flag must be connected to the ground plane with an array of vias as described in the analog layout guidelines table 3.8 power signals (continued) signal name type description
15kv esd protected mii/rmii 10/100 ethernet transceiver with hp auto-mdix support and flexpwr ? technology in a small footprint datasheet smsc lan8700/lan8700i 19 revision 2.3 (04-12-11) datasheet chapter 4 architecture details 4.1 top level functional architecture functionally, the phy can be divided into the following sections: ? 100base-tx transmit and receive ? 10base-t transmit and receive ? mii or rmii interface to the controller ? auto-negotiation to automatically dete rmine the best speed and duplex possible ? management control to read status r egisters and write control registers figure 4.1 100base-tx data path 4.2 100base-tx transmit the data path of the 100base-tx is shown in figure 4.1 . each major block is explained below. 4.2.1 100m transmit data ac ross the mii/rm ii interface for mii, the mac controller drives the transmit dat a onto the txd bus and asserts tx_en to indicate valid data. the data is latched by the phy?s mii block on the rising edge of tx_clk. the data is in the form of 4-bit wide 25mhz data. the mac controller drives the transmit data onto the txd bus and asserts tx_en to indicate valid data. the data is latched by the phy?s mii block on the rising edge of ref_clk. the data is in the form of 2-bit wide 50mhz data. 4.2.2 4b/5b encoding the transmit data passes from the mii block to th e 4b/5b encoder. this block encodes the data from 4-bit nibbles to 5-bit symbols (known as ?code-groups?) according to ta b l e 4 . 1 . each 4-bit data-nibble is mapped to 16 of the 32 possible code-groups. the remaining 16 code-groups are either used for control information or are not valid. mac tx driver mlt-3 converter nrzi converter 4b/5b encoder magnetics cat-5 rj45 25mhz by 5 bits nrzi mlt-3 mlt-3 mlt-3 mlt-3 scrambler and piso 125 mbps serial mii 25mhz by 4 bits tx_clk (for mii only) ext ref_clk (for rmii only) 100m pll m ii 25 m hz by 4 bits or rmii 50mhz by 2 bits
15kv esd protected mii/rmii 10/100 ethernet transceiver with hp auto-mdix support and flexpwr ? technology in a small footprint datasheet revision 2.3 (04-12-11) 20 smsc lan8700/lan8700i datasheet the first 16 code-groups are referred to by the hexadecimal values of their corresponding data nibbles, 0 through f. the remaining code-groups are given le tter designations with slashes on either side. for example, an idle code-group is /i/, a tr ansmit error code-group is /h/, etc. the encoding process may be bypassed by clearing bit 6 of register 31. when the encoding is bypassed the 5 th transmit data bit is equivalent to tx_er. note that encoding can be bypassed only when th e mac interface is configured to operate in mii mode. table 4.1 4b/5b code table code group sym receiver interpretation transmitter interpretation 11110 0 0 0000 data 0 0000 data 01001 1 1 0001 1 0001 10100 2 2 0010 2 0010 10101 3 3 0011 3 0011 01010 4 4 0100 4 0100 01011 5 5 0101 5 0101 01110 6 6 0110 6 0110 01111 7 7 0111 7 0111 10010 8 8 1000 8 1000 10011 9 9 1001 9 1001 10110 a a 1010 a 1010 10111 b b 1011 b 1011 11010 c c 1100 c 1100 11011 d d 1101 d 1101 11100 e e 1110 e 1110 11101 f f 1111 f 1111 11111 i idle sent after /t/r until tx_en 11000 j first nibble of ssd, translated to ?0101? following idle, else rx_er sent for rising tx_en 10001 k second nibble of ssd, translated to ?0101? following j, else rx_er sent for rising tx_en 01101 t first nibble of esd, causes de-assertion of crs if followed by /r/, else assertion of rx_er sent for falling tx_en 00111 r second nibble of esd, causes deassertion of crs if following /t/, else assertion of rx_er sent for falling tx_en 00100 h transmit error symbol sent for rising tx_er 00110 v invalid, rx_er if during rx_dv invalid
15kv esd protected mii/rmii 10/100 ethernet transceiver with hp auto-mdix support and flexpwr ? technology in a small footprint datasheet smsc lan8700/lan8700i 21 revision 2.3 (04-12-11) datasheet 4.2.3 scrambling repeated data patterns (especially the idle code-grou p) can have power spectral densities with large narrow-band peaks. scrambling the data helps eliminate these peaks and spread the signal power more uniformly over the entire channel bandwidth. this uniform spectral density is required by fcc regulations to prevent excessive emi fr om being radiated by the physical wiring. the seed for the scrambler is generated from the phy address, phyad[4:0], ensuring that in multiple- phy applications, such as repeaters or switc hes, each phy will have its own scrambler sequence. the scrambler also performs the parallel in serial out conversion (piso) of the data. 4.2.4 nrzi and mlt3 encoding the scrambler block passes the 5-bit wide parallel data to the nrzi converter where it becomes a serial 125mhz nrzi data stream. the nrzi is encoded to mlt-3. mlt3 is a tri-level code where a change in the logic level represents a code bit ?1? and the logic output remaining at the same level represents a code bit ?0?. 4.2.5 100m transmit driver the mlt3 data is then passed to the analog transmitter, which drives the differential mlt-3 signal, on outputs txp and txn, to the twisted pair media acro ss a 1:1 ratio isolation transformer. the 10base- t and 100base-tx signals pass through the same transformer so that common ?magnetics? can be used for both. the transmit ter drives into the 100 impedance of the cat-5 cable. cable termination and impedance matching require external components. 11001 v invalid, rx_er if during rx_dv invalid 00000 v invalid, rx_er if during rx_dv invalid 00001 v invalid, rx_er if during rx_dv invalid 00010 v invalid, rx_er if during rx_dv invalid 00011 v invalid, rx_er if during rx_dv invalid 00101 v invalid, rx_er if during rx_dv invalid 01000 v invalid, rx_er if during rx_dv invalid 01100 v invalid, rx_er if during rx_dv invalid 10000 v invalid, rx_er if during rx_dv invalid table 4.1 4b/5b code table (continued) code group sym receiver interpretation transmitter interpretation
15kv esd protected mii/rmii 10/100 ethernet transceiver with hp auto-mdix support and flexpwr ? technology in a small footprint datasheet revision 2.3 (04-12-11) 22 smsc lan8700/lan8700i datasheet 4.2.6 100m phase lock loop (pll) the 100m pll locks onto reference clock and genera tes the 125mhz clock used to drive the 125 mhz logic and the 100base-tx transmitter. figure 4.2 receive data path 4.3 100base-tx receive the receive data path is shown in figure 4.2 . detailed descriptions are given below. 4.3.1 100m receive input the mlt-3 from the cable is fed into the phy (on inputs rxp and rxn) via a 1:1 ratio transformer. the adc samples the incoming differential signal at a rate of 125m samples per second. using a 64- level quanitizer it generates 6 digital bits to repr esent each sample. the dsp adjusts the gain of the adc according to the observed signal levels such t hat the full dynamic range of the adc can be used. 4.3.2 equalizer, baseline wander corr ection and clock and data recovery the 6 bits from the adc are fed into the dsp bl ock. the equalizer in the dsp section compensates for phase and amplitude distortion caused by the ph ysical channel consisting of magnetics, connectors, and cat- 5 cable. the equalizer can restore the signal for any good-quality cat-5 cable between 1m and 150m. if the dc content of the signal is such that the low-frequency comp onents fall below the low frequency pole of the isolation transformer, then the dro op characteristics of t he transformer will become significant and baseline wander (blw) on the receiv ed signal will result. to prevent corruption of the received data, the phy corrects for blw and c an receive the ansi x3.263-1995 fddi tp-pmd defined ?killer packet? with no bit errors. the 100m pll generates multiple phas es of the 125mhz clock. a mult iplexer, controlled by the timing unit of the dsp, selects the optimum phase for sa mpling the data. this is used as the received recovered clock. this clock is used to ex tract the serial data from the received signal. mac a/d converter mlt-3 converter nrzi converter 4b/5b decoder magnetics cat-5 rj45 100m pll mii 25mhz by 4 bits or rmii 50mhz by 2 bits rx_clk (for mii only) 25mhz by 5 bits nrzi mlt-3 mlt-3 mlt-3 6 bit data descrambler and sipo 125 mbps serial dsp: timing recovery, equalizer and blw correction mlt-3 mii/rmii 25mhz by 4 bits ext ref_clk (for rmii only)
15kv esd protected mii/rmii 10/100 ethernet transceiver with hp auto-mdix support and flexpwr ? technology in a small footprint datasheet smsc lan8700/lan8700i 23 revision 2.3 (04-12-11) datasheet 4.3.3 nrzi and mlt-3 decoding the dsp generates the mlt-3 recovered levels that are fed to the mlt-3 converter. the mlt-3 is then converted to an nrzi data stream. 4.3.4 descrambling the descrambler performs an inverse function to t he scrambler in the transmitter and also performs the serial in parallel out (sipo) conversion of the data. during reception of idle (/i/) symbols. the descrambler synchron izes its descrambler key to the incoming stream. once synchronizati on is achieved, the descrambler locks on this key and is able to descramble incoming data. special logic in the descrambler ensures synchronization with the remote phy by searching for idle symbols within a window of 4000 bytes (40us). th is window ensures that a maximum packet size of 1514 bytes, allowed by the ieee 802. 3 standard, can be received with no interference. if no idle- symbols are detected within this time-period, rece ive operation is aborted and the descrambler re-starts the synchronization process. the descrambler can be bypassed by setting bit 0 of register 31. 4.3.5 alignment the de-scrambled signal is then aligned into 5-bit code-groups by recognizing the /j/k/ start-of-stream delimiter (ssd) pair at the start of a packet. once the code-word alignment is determined, it is stored and utilized until the next start of frame. 4.3.6 5b/4b decoding the 5-bit code-groups are translated into 4-bit da ta nibbles according to the 4b/5b table. the translated data is presented on th e rxd[3:0] signal lines. the ssd, /j/k/, is translated to ?0101 0101? as the first 2 nibbles of the mac preamble. reception of the ssd causes the phy to assert the rx_dv signal, indicating that valid data is available on the rxd bus. successive valid code-groups are translated to data nibbles. receptio n of either the end of stream delim iter (esd) consisting of the /t/r/ symbols, or at least two /i/ symbols causes the phy to de-assert carrier sense and rx_dv. these symbols are not translated into data. the decoding process may be bypassed by clearing bit 6 of register 31. when the decoding is bypassed the 5 th receive data bit is driven out on rx_er/rxd4. decoding may be bypassed only when the mac interface is in mii mode. 4.3.7 receive data valid signal the receive data valid signal (rx_dv) indicates that recovered and decoded nibbles are being presented on the rxd[3:0] outputs synchronous to rx_clk. rx_dv becomes active after the /j/k/ delimiter has been recognized and rxd is aligned to nibble boundaries. it remains active until either the /t/r/ delimiter is recognized or link test indicates failure or sigdet becomes false. rx_dv is asserted when the first nibble of trans lated /j/k/ is r eady for transfer over the media independent interface (mii mode).
15kv esd protected mii/rmii 10/100 ethernet transceiver with hp auto-mdix support and flexpwr ? technology in a small footprint datasheet revision 2.3 (04-12-11) 24 smsc lan8700/lan8700i datasheet figure 4.3 relationship between recei ved data and specific mii signals 4.3.8 receiver errors during a frame, unexpected code-groups are consid ered receive errors. expected code groups are the data set (0 through f), and the /t/r/ (esd) symbol pair. when a receive error occurs, the rx_er signal is asserted and arbitrary data is driven onto the rxd[3:0] lines. should an error be detected during the time that the /j/k/ delim iter is being decoded (bad ssd error), rx_er is asserted true and the value ?1110? is driven onto the rxd[3:0] lines. note that the valid data signal is not yet asserted when the bad ssd error occurs. 4.3.9 100m receive data across the mii/rmii interface in mii mode, the 4-bit data nibbles are sent to th e mii block. these data nibbles are clocked to the controller at a rate of 25mhz. the controller samples the data on the rising edge of rx_clk. to ensure that the setup and hold requirements are met, the nibbles are clocked out of the phy on the falling edge of rx_clk. rx_clk is the 25mhz output clock fo r the mii bus. it is re covered from the received data to clock the rxd bus. if there is no received signal, it is derived from the system reference clock (clkin). when tracking the received data, rx_clk has a maximum jitter of 0.8ns (provided that the jitter of the input clock, clkin, is below 100ps). in rmii mode, the 2-bit data nibbles are sent to the rmii block. these data nibbles are clocked to the controller at a rate of 50mhz. the controller samples the data on the rising edge of clkin/xtal1 (ref_clk). to ensure that the setup and hold requirements are met, the nibbles are clocked out of the phy on the falling edge of clkin/xtal1 (ref_clk). 4.4 10base-t transmit data to be transmitted comes from the mac layer co ntroller. the 10base-t transmitter receives 4-bit nibbles from the mii at a rate of 2.5mhz and converts them to a 10mbps serial data stream. the data stream is then manchester-encoded and sent to the analog transmitter, which drives a signal onto the twisted pair via the external magnetics. the 10m transmitter uses the following blocks: ? mii (digital) ? tx 10m (digital) ? 10m transmitter (analog) ? 10m pll (analog) 4.4.1 10m transmit data ac ross the mii/rmii interface the mac controller drives the tran smit data onto the txd bus. for mii, when the controller has driven tx_en high to indicate valid data, the data is latched by the mii block on the rising edge of tx_clk. the data is in the form of 4-bit wide 2.5mhz data. 5d 5 data data data data rxd rx_dv rx_clk 5d 5 data data data data clear-text 5 jk 5 55 tr idle
15kv esd protected mii/rmii 10/100 ethernet transceiver with hp auto-mdix support and flexpwr ? technology in a small footprint datasheet smsc lan8700/lan8700i 25 revision 2.3 (04-12-11) datasheet in order to comply with legacy 10base-t mac/cont rollers, in half-duplex mode the phy loops back the transmitted data, on the receive path. this d oes not confuse the mac/ controller since the col signal is not asserted during this time. the phy also supports the sqe (heartbeat) signal. see section 5.4.2, "collision detect," on page 51 , for more details. for rmii, txd[1:0] shall transition synchronously with respect to ref_clk. when tx_en is asserted, txd[1:0] are accepted for transm ission by the lan8700/lan8700i. txd[1:0] shall be ?00? to indicate idle when tx_en is deasserted. va lues of txd[1:0] othe r than ?00? when tx_en is deasserted are reserved for out-of-band signalling (to be defined). va lues other than ?00? on txd[1:0] while tx_en is deasserted shall be ignored by the lan8700/lan8700i.txd[1:0] shall provide valid data for each ref_clk period while tx_en is asserted. 4.4.2 manchester encoding the 4-bit wide data is sent to the tx10m block. th e nibbles are converted to a 10mbps serial nrzi data stream. the 10m pll locks onto the external cl ock or internal oscillator and produces a 20mhz clock. this is used to manchester encode the nrz data stream. when no data is being transmitted (tx_en is low), the tx10m block outputs normal link pulses (nlps) to maintain communications with the remote link partner. 4.4.3 10m transmit drivers the manchester encoded data is sent to the anal og transmitter where it is shaped and filtered before being driven out as a differential signal across the txp and txn outputs. 4.5 10base-t receive the 10base-t receiver gets the manchester- encoded analog signal from the cable via the magnetics. it recovers the receive clock from the signal and uses this clock to recover the nrzi data stream. this 10m serial data is converted to 4-bit data nibbles which are passed to the controller across the mii at a rate of 2.5mhz. this 10m receiver uses the following blocks: ? filter and squelch (analog) ? 10m pll (analog) ? rx 10m (digital) ? mii (digital) 4.5.1 10m receive input and squelch the manchester signal from the cable is fed into the phy (on inputs rxp and rxn) via 1:1 ratio magnetics. it is first filtered to reduce any out-of-band noise. it then passes through a squelch circuit. the squelch is a set of amplitude and timi ng comparators that norma lly reject differential voltage levels below 300mv and detect and re cognize differential voltages above 585mv. 4.5.2 manchester decoding the output of the squelch goes to the rx10m block where it is validated as manchester encoded data. the polarity of the signal is also checked. if the polarity is reversed (local rxp is connected to rxn of the remote partner and vice versa), then this is identified and corrected. the reversed condition is indicated by the flag ?xpol?, bit 4 in register 27. the 10m pll is locked onto the received manchester signal and from this, generates the received 20mhz clock. using this clock, the manchester encoded data is extracted and conver ted to a 10mhz nrzi dat a stream. it is then converted from serial to 4-bit wide parallel data.
15kv esd protected mii/rmii 10/100 ethernet transceiver with hp auto-mdix support and flexpwr ? technology in a small footprint datasheet revision 2.3 (04-12-11) 26 smsc lan8700/lan8700i datasheet the rx10m block also detects valid 10base-t idle signals - normal link pulses (nlps) - to maintain the link. 4.5.3 10m receive data across the mii/rmii interface for mii, the 4 bit data nibbles are sent to the mii block. in mii mode, these data nibbles are valid on the rising edge of the 2.5 mhz rx_clk. for rmii, the 2bit data nibbles are s ent to the rmii block. in rmii mode, these data nibbles are valid on the rising edge of the rmii ref_clk. 4.5.4 jabber detection jabber is a condition in which a station transmits for a period of time longer than the maximum permissible packet length, usually due to a fault condi tion, that results in ho lding the tx_en input for a long period. special logic is used to detect the jabber state and abort the transmission to the line, within 45ms. once tx_en is deasserted, the logic resets the jabber condition. as shown in ta b l e 5 . 3 1 , bit 1.1 indicates that a jabber condition was detected. 4.6 mac interface the mii/rmii block is responsible fo r the communication with the controller. special sets of hand-shake signals are used to indicate that valid received/tra nsmitted data is present on the 4 bit receive/transmit bus. the device must be configured in mii or rmii mode. see section 4.6.3, "mii vs . rmii configuration," on page 28 . 4.6.1 mii the mii includes 16 interface signals: ? transmit data - txd[3:0] ? transmit strobe - tx_en ? transmit clock - tx_clk ? transmit error - tx_er/txd4 ? receive data - rxd[3:0] ? receive strobe - rx_dv ? receive clock - rx_clk ? receive error - rx_er/rxd4 ? collision indication - col ? carrier sense - crs in mii mode, on the transmit path, the phy drives the transmit clock, tx_clk , to the controller. the controller synchronizes the transmit data to the rising edge of tx_clk. the controller drives tx_en high to indicate valid transmit data. the controller drives tx_er high when a transmit error is detected. on the receive path, the phy drives both the re ceive data, rxd[3:0], and the rx_clk signal. the controller clocks in the receive data on the risi ng edge of rx_clk when the phy drives rx_dv high. the phy drives rx_er high when a receive error is detected.
15kv esd protected mii/rmii 10/100 ethernet transceiver with hp auto-mdix support and flexpwr ? technology in a small footprint datasheet smsc lan8700/lan8700i 27 revision 2.3 (04-12-11) datasheet 4.6.2 rmii the smsc lan8700/lan8700i supports the low pin count reduced media independent interface (rmii) intended for use between ethernet phys and switch asics. under ieee 802.3, an mii comprised of 16 pins for data and control is defin ed. in devices incorporating many macs or phy interfaces such as switches, the number of pins can add significant cost as the port counts increase. the management interface (mdio/mdc) is identica l to mii. the rmii interface has the following characteristics: ? it is capable of supporting 10mb/s and 100mb/s data rates ? a single clock reference is sourced from th e mac to phy (or from an external source) ? it provides independent 2 bit wide (di-bit) transmit and receive data paths ? it uses lvcmos signal levels, compatib le with common digital cmos asic processes the rmii includes 6 interface signals with one of the signals being optional: ? transmit data - txd[1:0] ? transmit strobe - tx_en ? receive data - rxd[1:0] ? receive error - rx_er (optional) ? carrier sense - crs_dv ? reference clock - clkin/xtal1 (rmii referenc es usually define this signal as ref_clk) 4.6.2.1 reference clock the reference clock - clkin, is a continuous clock that provides the timing reference for crs_dv, rxd[1:0], tx_en, txd[1:0], and rx_er. the refere nce clock is sourced by the mac or an external source. switch implementations may choose to provide ref_clk as an in put or an output depending on whether they provide a ref_clk output or re ly on an external clock distribution device. the ?reference clock? frequency must be 50 mh z 50 ppm with a duty cycle between 40% and 60% inclusive. the smsc lan8700/lan8700i uses the ?ref erence clock? as the network clock such that no buffering is required on the transmit data path. the smsc lan8700/lan8700i will recover the clock from the incoming data stream, the receiver will account for differences between the local ref_clk and the recovered clock through use of sufficient elasticity buffering. the elasticity buffer does not affect the inter-packet gap (ipg) for received ipgs of 36 bits or greater. to tolerate the clock variations specified here for ethernet mtus, the elasticity buffer shall tolerate a minimum of 10 bits. 4.6.2.2 crs_dv - carrier sense/receive data valid the crs_dv is asserted by the lan8700/lan8700i when the receive medium is non-idle. crs_dv is asserted asynchronously on detection of carrier d ue to the criteria releva nt to the operating mode. that is, in 10base-t mode, when squelch is pa ssed or in 100base-x mode when 2 non-contiguous zeroes in 10 bits are detected, carrier is said to be detected. loss of carrier shall result in the deassertion of crs_dv synchronous to the cycle of ref_clk which presents the first di-bit of a nibble onto rxd[1:0] (i.e. crs_dv is deasserted only on nibble boundaries). if the lan8700/lan8700i has additional bits to be presented on rxd[1:0] following the initial deassertion of crs_dv, then the lan8 700/lan8700i shall assert crs_dv on cycles of ref_clk which present the second di-bit of each nibble and de-assert crs_dv on cycles of ref_clk which present the first di -bit of a nibble. the result is: starting on nibble boundaries crs_dv toggles at 25 mhz in 100mb/s mode and 2.5 mhz in 10mb/s mode when crs ends before rx_dv (i.e. the fifo still has bits to transfer wh en the carrier event ends.) therefore, the mac can accurately recover rx_dv and crs. during a false carrier event, crs_dv shall remain asserted for the duration of carrier activity. the data on rxd[1:0] is considered valid once crs_dv is as serted. however, since the assertion of crs_dv
15kv esd protected mii/rmii 10/100 ethernet transceiver with hp auto-mdix support and flexpwr ? technology in a small footprint datasheet revision 2.3 (04-12-11) 28 smsc lan8700/lan8700i datasheet is asynchronous relative to ref_clk, the data on rxd[1:0] shall be ?00? until proper receive signal decoding takes place. 4.6.3 mii vs. rmii configuration the lan8700/lan8700i must be configured to support th e mii or rmii bus for connectivity to the mac. this configuration is done through the col/rmii/crs_dv pin. to select mii mode, float the col/rmii/crs_dv pin. to select rmii mode, pu ll the pin high with an external resistor (see ta b l e 4 . 3 , ?boot strapping configuration resistors,? on page 33 ) to vddio. on the rising edge of the internal reset (nreset), the regi ster bit 18.14 (miimode) is loaded based on the strapping of the col/rmii/crs_dv pin. most of the mii and rmii pins are multiplexed. table 4.2, "mii/rmii signal mapping" , shown below, describes the relationship of the related device pi ns to what pins are used in mii and rmii mode. note 4.1 in rmii mode, this pin needs to tied to vss. note 4.2 the rx_er signal is optional on the rmii bus. this signal is required by the phy, but it is optional for the mac. the mac can choose to ignore or not use this signal. table 4.2 mii/rmii signal mapping signal name mii mode rmii mode txd0 txd0 txd0 txd1 txd1 txd1 tx_en tx_en tx_en rx_er/ rxd4 rx_er/ rxd4/ rx_er note 4.2 col/rmii/crs_dv col crs_dv rxd0 rxd0 rxd0 rxd1 rxd1 rxd1 txd2 txd2 note 4.1 txd3 txd3 note 4.1 tx_er/ txd4 tx_er/ txd4 crs crs rx_dv rx_dv rxd2 rxd2 rxd3/ nintsel rxd3 tx_clk tx_clk rx_clk rx_clk clkin/xtal1 clkin/xtal1 ref_clk
15kv esd protected mii/rmii 10/100 ethernet transceiver with hp auto-mdix support and flexpwr ? technology in a small footprint datasheet smsc lan8700/lan8700i 29 revision 2.3 (04-12-11) datasheet 4.7 auto-negotiation the purpose of the auto-negotiation function is to automatically configure the phy to the optimum link parameters based on the capabilities of its li nk partner. auto-negotiation is a mechanism for exchanging configuration information between two lin k-partners and automatically selecting the highest performance mode of operation supported by both si des. auto-negotiation is fully defined in clause 28 of the ieee 802.3 specification. once auto-negotiation has completed, information ab out the resolved link can be passed back to the controller via the serial management interface (smi). the results of the negotiation process are reflected in the speed indication bits in register 31, as well as the link partner ability register (register 5). the auto-negotiation protocol is a purely physical layer activity and proceeds independently of the mac controller. the advertised capabilities of the phy are stored in register 4 of the sm i registers. the default advertised by the phy is determined by user-defined on-chip signal options. the following blocks are activated during an auto-negotiation session: ? auto-negotiation (digital) ? 100m adc (analog) ? 100m pll (analog) ? 100m equalizer/blw/clock recovery (dsp) ? 10m squelch (analog) ? 10m pll (analog) ? 10m transmitter (analog) when enabled, auto-negotiation is started by t he occurrence of one of the following events: ? hardware reset ? software reset ? power-down reset ? link status down ? setting register 0, bit 9 high (auto-negotiation restart) on detection of one of these event s, the phy begins auto-negotiation by transmitting bursts of fast link pulses (flp). these are bur sts of link pulses from the 10m transmitter. they are shaped as normal link pulses and can pass uncorrupted down cat-3 or cat-5 cable. a fast link pulse burst consists of up to 33 pulses. the 17 odd-number ed pulses, which are always present, frame the flp burst. the 16 even-numbered pulses, which may be present or absent, cont ain the data word being transmitted. presence of a data pulse repres ents a ?1?, while absence represents a ?0?. the data transmitted by an flp burst is known as a ?link code word.? these are defined fully in ieee 802.3 clause 28. in summary, the phy advertises 8 02.3 compliance in its selector field (the first 5 bits of the link code word). it advertises its technology abi lity according to the bits set in register 4 of the smi registers. there are 4 possible matches of the technology ab ilities. in the order of priority these are: ? 100m full duplex (highest priority) ? 100m half duplex ? 10m full duplex ? 10m half duplex
15kv esd protected mii/rmii 10/100 ethernet transceiver with hp auto-mdix support and flexpwr ? technology in a small footprint datasheet revision 2.3 (04-12-11) 30 smsc lan8700/lan8700i datasheet if the full capabilities of the phy are advertised (1 00m, full duplex), and if the link partner is capable of 10m and 100m, then auto-negotiation selects 1 00m as the highest performance mode. if the link partner is capable of half and full duplex modes, then auto-negotiation selects full duplex as the highest performance operation. once a capability match has been determined, the link code words are repeated with the acknowledge bit set. any difference in the main content of the link code words at this time will cause auto-negotiation to re-start. auto-negotiation will also re-start if not all of the required flp bursts are received. the capabilities advertised during auto-negotiation by the phy are initially determined by the logic levels latched on the mode[2:0] bus after reset completes. this bus can also be used to disable auto- negotiation on power-up. writing register 4 bits [8:5] allows software control of the capabilities advertised by the phy. writing register 4 does not automatically re -start auto-negotiation. register 0, bit 9 must be set before the new abilities will be advertised. auto-negotiation can also be disabled via software by clearing register 0, bit 12. the lan8700/lan8700i does not support ?next page? capability. 4.7.1 parallel detection if the lan8700/lan8700i is connected to a devic e lacking the ability to auto-negotiate (i.e. no flps are detected), it is able to determine the speed of the link based on either 100m mlt-3 symbols or 10m normal link pulses. in this case the link is presumed to be half duplex per the ieee standard. this ability is known as ?parallel detection.? th is feature ensures interoperability with legacy link partners. if a link is formed via para llel detection, then bit 0 in register 6 is cleared to indicate that the link partner is not capable of auto-negotiation. the controller has access to this information via the management interface. if a fault occurs during pa rallel detection, bit 4 of register 6 is set. register 5 is used to store the link partner abilit y information, which is coded in the received flps. if the link partner is not auto-negotiation capable, then register 5 is updated after completion of parallel detection to reflect the speed capability of the link partner. 4.7.2 re-starting auto-negotiation auto-negotiation can be re-started at any time by sett ing register 0, bit 9. auto-negotiation will also re- start if the link is broken at any time. a broken link is caused by signal loss. this may occur because of a cable break, or because of an interruption in the signal transmitted by the link partner. auto- negotiation resumes in an attempt to determine the new link configuration. if the management entity re-starts au to-negotiation by writing to bi t 9 of the control register, the lan8700/lan8700i will respond by stopping all tr ansmission/receiving operations. once the break_link_timer is done, in the auto-negotiation state-machine (approximately 1200ms) the auto- negotiation will re-start. the link partner will have also dropped the link due to lack of a received signal, so it too will resume auto-negotiation. 4.7.3 disabling auto-negotiation auto-negotiation can be disabled by setting regist er 0, bit 12 to zero. the device will then force its speed of operation to reflect the information in regist er 0, bit 13 (speed) and register 0, bit 8 (duplex). the speed and duplex bits in register 0 should be ignored when auto-negotiation is enabled. 4.7.4 half vs. full duplex half duplex operation relies on the csma/cd (car rier sense multiple access / collision detect) protocol to handle network traffic and collisions. in this mode, the carrier sense signal, crs, responds to both transmit and receive activity. in this mode, if data is received while the phy is transmitting, a collision results.
15kv esd protected mii/rmii 10/100 ethernet transceiver with hp auto-mdix support and flexpwr ? technology in a small footprint datasheet smsc lan8700/lan8700i 31 revision 2.3 (04-12-11) datasheet in full duplex mode, the phy is able to transmit and receive data simultaneously. in this mode, crs responds only to receive activity. the csma/cd pr otocol does not apply and collision detection is disabled. 4.8 hp auto-mdix hp auto-mdix facilitates the use of cat-3 (10 base -t) or cat-5 (100 base-t ) media utp interconnect cable without consideration of inte rface wiring scheme. if a user plugs in either a direct connect lan cable, or a cross-over patch cable, as shown in figure 4.4 on page 31 , the smsc lan8700/lan8700i auto-mdix phy is capable of configuring the tx p/txn and rxp/rxn pins for correct transceiver operation. the internal logic of the device detects the tx and rx pins of the connecting device. since the rx and tx line pairs are interchangeable, special pcb design considerations are needed to accommodate the symmetrical magnetics and termination of an auto-mdix design. the auto-mdix function can be disabled through an internal register. 4.9 internal +1.8v regulator disable one feature of the flexpwr technology is the ability to configure the internal 1.8v regulator off. when the regulator is disabled, external 1.8v must be supplied to vdd_core. this makes it possible to reduce total system power, since an external switching regulator with greate r efficiency than the internal linear regulator may be used to provide the +1.8v to the phy circuitry. 4.9.1 disable the internal +1.8v regulator to disable the +1.8v internal regulator, a pullup strapping resistor (see table 4.3, ?boot strapping configuration resistors,? on page 33 ) is connected from rxclk/re goff to vddio. at power-on, after both vddio and vdda are wit hin specification, the phy will sample the rxclk/regoff pin to determine if the internal regulator should turn on. if the pin is sampled at a voltage greater than v ih , then the internal regulator is disabled, and the s ystem must supply +1.8v to the vdd_core pin. the voltage at vdd33 must be at least 2.64v (0.8 * 3.3v) before voltage is applied to vdd_core. as described in section 4.9.2 , when the rxclk/regoff pin is left floating or connected to vss, then the internal re gulator is enabled and the system does not supply +1.8v to the vdd_core pin. figure 4.4 direct cable connection vs. cross-over cable connection.
15kv esd protected mii/rmii 10/100 ethernet transceiver with hp auto-mdix support and flexpwr ? technology in a small footprint datasheet revision 2.3 (04-12-11) 32 smsc lan8700/lan8700i datasheet when the +1.8v internal regulator is disabled, a 0.1uf capacitor must be added at the vdd_core pin and placed close to the phy to decouple the external power supply. 4.9.2 enable the internal +1.8v regulator the 1.8v for vdd_core is supplied by the on-ch ip regulator unless the phy is configured for regulator off mode using the rx_clk/regoff pin as described in section 4.9.1 . by default, the internal +1.8v regulator is enabled when the rxclk/regoff pin is floating. as shown in ta b l e 7 . 11 , an internal pull-down resistor straps the regulat or on if the rxclk/regoff pin is floating. during vddio and vdda power-on, if t he rxclk/regoff pin is sampled below v il , then the internal +1.8v regulator will turn on and ope rate with power from the vdd33 pin. when using the internal linear regulator, a 4.7uf bypass capacitor with esr < 1ohm and a 0.1uf capacitor must always be added to vdd_core and pl aced close to the phy to ensure stability of the internal regulator. 4.10 nint/tx_er/txd4 strapping the nint, tx_er, and txd4 functions share a comm on pin. there are two functional modes for this pin, the tx_er/txd4 mode and nint (interrupt) mo de. the rxd3/nintsel pin is used to select one of these two functional modes. the rxd3/nintsel pin is latched on the rising edge of the nrst . the system designer must float the nintsel pin to put the nint/tx_er/txd4 pin into nint mode or pull-low to vss with an external resistor (see table 4.3, ?boot strapping configuration resistors,? on page 33 ) to set the device in tx_er/txd4 mode. the default setting is to float the pin high for nint mode. 4.11 phy address strapping and led output polarity selection the phy address bits are latched on the rising edge of the internal reset (nreset). the 5-bit address word[0:4] is input on the phyad[0:4] pi ns. the default setting is all high 5'b1_1111. the address lines are strapped as defined in the diagram below. the led outputs will automatically change polarity based on the presen ce of an external pull-down resi stor. if the led pin is pulled high (by an internal 100k pull-up resistor) to select a logical high phy address, then the led output will be active low. if the led pin is pulled low (by an external pull-down resistor (see table 4.3, ?boot strapping configuration resistors,? on page 33 ) to select a logical low phy address, the led output will then be an active high output. to set the phy address on the led pins without leds or on the crs pin, float the pin to set the address high or pull-down the pin with an external resistor (see table 4.3, ?boot strapping configuration resistors,? on page 33 ) to gnd to set the address low. see figure 4.5, "phy address strapping on led?s":
15kv esd protected mii/rmii 10/100 ethernet transceiver with hp auto-mdix support and flexpwr ? technology in a small footprint datasheet smsc lan8700/lan8700i 33 revision 2.3 (04-12-11) datasheet figure 4.5 phy address strapping on led?s 4.12 variable voltage i/o the digital i/o pins on the lan8700/lan8700i are variable voltage to take advantage of low power savings from shrinking technologies. these pins c an operate from a low i/o voltage of +1.8v-10% up to +3.3v+10%. due to this low voltage feat ure addition, the system designer needs to take consideration as for two aspects of their design. bo ot strapping configuration and i/o voltage stability. 4.12.1 boot strappi ng configuration due to a lower i/o voltage, a lower strapping resistor needs to be used to ensure the strapped configuration is latched into th e phy device at power-on reset. . 4.12.2 i/o voltage stability the i/o voltage the system designer applies on vddi o needs to maintain its value with a tolerance of 10%. varying the voltage up or down, after the phy has completed power-on reset can cause errors in the phy operation. 4.13 phy management control the management control module includes 3 blocks: ? serial management interface (smi) ? management registers set ? interrupt table 4.3 boot strapping configuration resistors i/o voltage pull-up/pull-down resistor 3.0 to 3.6 10k ohm resistor 2.0 to 3.0 7.5k ohm resistor 1.6 to 2.0 5k ohm resistor led1-led4 ~270 ohms phy address = 0 led output = active high ~10k ohms ~270 ohms led1-led4 vdd phy address = 1 led output = active low
15kv esd protected mii/rmii 10/100 ethernet transceiver with hp auto-mdix support and flexpwr ? technology in a small footprint datasheet revision 2.3 (04-12-11) 34 smsc lan8700/lan8700i datasheet 4.13.1 serial management interface (smi) the serial management interface is used to contro l the lan8700/lan8700i and obtain its status. this interface supports registers 0 through 6 as require d by clause 22 of the 802.3 standard, as well as ?vendor-specific? registers 16 to 31 allowed by the specification. non-supported registers (7 to 15) will be read as hexadecimal ?ffff?. at the system level there are 2 si gnals, mdio and mdc where mdio is bi-directional open-drain and mdc is the clock. a special feature (enabled by register 17 bit 3) forces the phy to disregard the phy-address in the smi packet causing the phy to respond to any address. this feature is useful in multi-phy applications and in production testing, where the same register can be written in all the phys using a single write transaction. the mdc signal is an aperiodic clock provided by the station management controller (smc). the mdio signal receives serial data (commands) from the contro ller smc, and sends serial data (status) to the smc. the minimum time between edges of the mdc is 160 ns. there is no maximum time between edges. the minimum cycle time (time between two consecutive rising or two consecutive falling edges) is 400 ns. these modest timing requirements allow this inte rface to be easily driven by the i/o port of a microcontroller. the data on the mdio line is latched on the rising edge of the mdc. the frame structure and timing of the data is shown in figure 4.6 and figure 4.7 . the timing relationships of the mdio signals are further described in section 6.1, "serial management interface (smi) timing," on page 57 . figure 4.6 mdio timing and frame structure - read cycle figure 4.7 mdio timing and frame structure - write cycle mdc mdi0 read cycle ... 32 1's 0110a4a3a2a1a0r4r3r2r1r0 d1 ... d15 d14 d0 preamble start of frame op code phy address register address turn around data data from phy data to phy mdc mdio ... 32 1's 0 1 1 0 a4a3a2a1a0r4r3r2r1r0 write cycle d15 d14 d1 d0 ... data preamble start of frame op code phy address register address turn around data to phy
15kv esd protected mii/rmii 10/100 ethernet transceiver with hp auto-mdix support and flexpwr ? technology in a small footprint datasheet revision 2.3 (04-12-11) 35 smsc lan8700/lan8700i datasheet chapter 5 registers table 5.1 control register: register 0 (basic) 15 14 13 12 11 10 9 8 7 6543210 reset loopback speed select a/n enable power down isolate restart a/n duplex mode collision test reserved table 5.2 status register: register 1 (basic) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 100base- t4 100base- tx full duplex 100base- tx half duplex 10base-t full duplex 10base-t half duplex reserved a/n complete remote fault a/n ability link status jabber detect extended capability table 5.3 phy id 1 register: register 2 (extended) 1514131211109876543210 phy id number (bits 3-18 of the organizationally unique identifier - oui) table 5.4 phy id 2 register: register 3 (extended) 1514131211109876543210 phy id number (bits 19-24 of the organizationally unique identifier - oui) manufacturer model number manufacturer revision number table 5.5 auto-negotiation advertisement: register 4 (extended) 15 14 13 12 11 10 9 8 7 6 5 43210 next page reserved remote fault reserved pause operation 100base- t4 100base- tx full duplex 100base- tx 10base-t full duplex 10base-t ieee 802.3 selector field
15kv esd protected mii/rmii 10/100 ethernet transceiver with hp auto-mdix support and flexpwr ? technology in a small footprint datasheet revision 2.3 (04-12-11) 36 smsc lan8700/lan8700i datasheet note: next page capability is not supported . table 5.6 auto-negotiation link partner base page ability register: register 5 (extended) 15 14 13 1211 10 9 8 7 6 5 43210 next page acknowledge remote fault reserved pause 100base- t4 100base-tx full duplex 100base- tx 10base-t full duplex 10base- t ieee 802.3 selector field table 5.7 auto-negotiation expans ion register: register 6 (extended) 15141312111098765 4 3 2 1 0 reserved parallel detect fault link partner next page able next page able page received link partner a/n able table 5.8 auto-negotiation link partner next page transmit register: register 7 (extended) 1514131211109876543210 reserved
15kv esd protected mii/rmii 10/100 ethernet transceiver with hp auto-mdix support and flexpwr ? technology in a small footprint datasheet revision 2.3 (04-12-11) 37 smsc lan8700/lan8700i datasheet table 5.9 register 8 (extended) 1514131211109876543210 ieee reserved table 5.10 register 9 (extended) 1514131211109876543210 ieee reserved table 5.11 register 10 (extended) 1514131211109876543210 ieee reserved table 5.12 register 11 (extended) 1514131211109876543210 ieee reserved table 5.13 register 12 (extended) 1514131211109876543210 ieee reserved table 5.14 register 13 (extended) 1514131211109876543210 ieee reserved
15kv esd protected mii/rmii 10/100 ethernet transceiver with hp auto-mdix support and flexpwr ? technology in a small footprint datasheet revision 2.3 (04-12-11) 38 smsc lan8700/lan8700i datasheet rsvd = reserved table 5.15 register 14 (extended) 1514131211109876543210 ieee reserved table 5.16 register 15 (extended) 1514131211109876543210 ieee reserved table 5.17 silicon revision register 16: vendor-specific 1514131211109876543210 reserved silicon revision reserved table 5.18 mode control/ status register 17: vendor-specific 1 5 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rsvd edpwrdown rsvd lowsqen mdprebp farloopback rsvd altint rsvd phyadbp force good link status energyon rsvd table 5.19 special modes register 18: vendor-specific 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved miimode reserved mode phyad
15kv esd protected mii/rmii 10/100 ethernet transceiver with hp auto-mdix support and flexpwr ? technology in a small footprint datasheet revision 2.3 (04-12-11) 39 smsc lan8700/lan8700i datasheet table 5.20 reserved register 19: vendor-specific 1514131211109876543210 reserved table 5.21 register 24: vendor-specific 1514131211109876543210 reserved table 5.22 register 25: vendor-specific 1514131211109876543210 reserved table 5.23 symbol error counter register 26: vendor-specific 1514131211109876543210 symbol error counter table 5.24 special control/status indi cations register 27: vendor-specific 15 14 13 12 11 10 98765 4 3210 amdixctrl reserved ch_ select reserved sqeoff reserved xpol reserved table 5.25 special internal testabilit y control register 28: vendor-specific 1514131211109876543210 reserved
15kv esd protected mii/rmii 10/100 ethernet transceiver with hp auto-mdix support and flexpwr ? technology in a small footprint datasheet revision 2.3 (04-12-11) 40 smsc lan8700/lan8700i datasheet table 5.26 interrupt source flags register 29: vendor-specific 151413121110987654321 0 reserved int7 int6 int5 int4 int3 int2 int1 reserved table 5.27 interrupt mask register 30: vendor-specific 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved mask bits reserved table 5.28 phy special control/status register 31: vendor-specific 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved autodone reserved enable 4b5b reserved speed indication reserved scramble disable
15kv esd protected mii/rmii 10/100 ethernet transceiver with hp auto-mdix support and flexpwr ? technology in a small footprint datasheet smsc lan8700/lan8700i 41 revision 2.3 (04-12-11) datasheet 5.1 smi register mapping the following registers are supported (register numbers are in decimal): 5.2 smi register format the mode key is as follows: ? rw = read/write, ? sc = self clearing, ? wo = write only, ? ro = read only, ? lh = latch high, clear on read of register, ? ll = latch low, clear on read of register, ? nasr = not affected by software reset ? x = either a 1 or 0. table 5.29 smi register mapping register # description group 0 basic control register basic 1 basic status register basic 2 phy identifier 1 extended 3 phy identifier 2 extended 4 auto-negotiation advert isement register extended 5 auto-negotiation link partner ability register extended 6 auto-negotiation expansion register extended 16 silicon revision register vendor-specific 17 mode control/status register vendor-specific 18 special modes vendor-specific 20 reserved vendor-specific 21 reserved vendor-specific 22 reserved vendor-specific 23 reserved vendor-specific 26 symbol error counter register vendor-specific 27 control / status indica tion register vendor-specific 28 special internal testability controls vendor-specific 29 interrupt source register vendor-specific 30 interrupt mask register vendor-specific 31 phy special control/stat us register vendor-specific
15kv esd protected mii/rmii 10/100 ethernet transceiver with hp auto-mdix support and flexpwr ? technology in a small footprint datasheet revision 2.3 (04-12-11) 42 smsc lan8700/lan8700i datasheet table 5.30 register 0 - basic control address name description mode default 0.15 reset 1 = software reset. bit is self-clearing. for best results, when setting this bit do not set other bits in this register. the configuration (as described in section 5.4.9.2 ) is set from the register bit values, and not from the mode pins. rw/ sc 0 0.14 loopback 1 = loopback mode, 0 = normal operation rw 0 0.13 speed select 1 = 100mbps, 0 = 10mbps. ignored if auto negotiation is enabled (0.12 = 1). rw set by mode[2:0] bus 0.12 auto- negotiation enable 1 = enable auto-negotiate process (overrides 0.13 and 0.8) 0 = disable auto-negotiate process rw set by mode[2:0] bus 0.11 power down 1 = general power down mode, 0 = normal operation rw 0 0.10 isolate 1 = electrical isolation of phy from mii 0 = normal operation rw 0 0.9 restart auto- negotiate 1 = restart auto-negotiate process 0 = normal operation. bit is self-clearing. rw/ sc 0 0.8 duplex mode 1 = full duplex, 0 = half duplex. ignored if auto negotiation is enabled (0.12 = 1). rw set by mode[2:0] bus 0.7 collision test 1 = enable col test, 0 = disable col test rw 0 0.6:0 reserved ro 0 table 5.31 register 1 - basic status address name description mode default 1.15 100base-t4 1 = t4 able, 0 = no t4 ability ro 0 1.14 100base-tx full duplex 1 = tx with full duplex, 0 = no tx full duplex ability ro 1 1.13 100base-tx half duplex 1 = tx with half duplex, 0 = no tx half duplex ability ro 1 1.12 10base-t full duplex 1 = 10mbps with full duplex 0 = no 10mbps with full duplex ability ro 1 1.11 10base-t half duplex 1 = 10mbps with half duplex 0 = no 10mbps with half duplex ability ro 1 1.10:6 reserved 1.5 auto-negotiate complete 1 = auto-negotiate process completed 0 = auto-negotiate process not completed ro 0
15kv esd protected mii/rmii 10/100 ethernet transceiver with hp auto-mdix support and flexpwr ? technology in a small footprint datasheet smsc lan8700/lan8700i 43 revision 2.3 (04-12-11) datasheet 1.4 remote fault 1 = remote fault condition detected 0 = no remote fault ro/ lh 0 1.3 auto-negotiate ability 1 = able to perform auto-negotiation function 0 = unable to perform auto-negotiation function ro 1 1.2 link status 1 = link is up, 0 = link is down ro/ ll x 1.1 jabber detect 1 = jabber condition detected 0 = no jabber condition detected ro/ lh x 1.0 extended capabilities 1 = supports extended capabilities registers 0 = does not support extende d capabilities registers ro 1 table 5.32 register 2 - phy identifier 1 address name description mode default 2.15:0 phy id number assigned to the 3rd through 18th bits of the organizationally unique ident ifier (oui), respectively. oui=00800fh rw 0007h table 5.33 register 3 - phy identifier 2 address name description mode default 3.15:10 phy id number assigned to the 19 th through 24 th bits of the oui. rw c0h 3.9:4 model number six-bit manufacturer?s model number. rw 0ch 3.3:0 revision number four-bit manufacturer?s revision number. rw 4h table 5.34 register 4 - auto negotiation advertisement address name description mode default 4.15 next page 1 = next page capable, 0 = no next page ability this phy does not support next page ability. ro 0 4.14 reserved ro 0 4.13 remote fault 1 = remote fault detected, 0 = no remote fault rw 0 4.12 reserved 4.11:10 pause operation 00 = no pause 01 = symmetric pause 10 = asymmetric pause toward link partner 11 = both symmetric pause and asymmetric pause toward local device r/w 00 table 5.31 register 1 - basic status (continued) address name description mode default
15kv esd protected mii/rmii 10/100 ethernet transceiver with hp auto-mdix support and flexpwr ? technology in a small footprint datasheet revision 2.3 (04-12-11) 44 smsc lan8700/lan8700i datasheet 4.9 100base-t4 1 = t4 able, 0 = no t4 ability this phy does not support 100base-t4. ro 0 4.8 100base-tx full duplex 1 = tx with full duplex, 0 = no tx full duplex ability rw set by mode[2:0] bus 4.7 100base-tx 1 = tx able, 0 = no tx ability rw 1 4.6 10base-t full duplex 1 = 10mbps with full duplex 0 = no 10mbps with full duplex ability rw set by mode[2:0] bus 4.5 10base-t 1 = 10mbps able, 0 = no 10mbps ability rw set by mode[2:0] bus 4.4:0 selector field [000 01] = ieee 802.3 rw 00001 table 5.35 register 5 - auto negotiation link partner ability address name description mode default 5.15 next page 1 = ?next page? capable, 0 = no ?next page? ability this phy does not support next page ability. ro 0 5.14 acknowledge 1 = link code word received from partner 0 = link code word not yet received ro 0 5.13 remote fault 1 = remote fault detected, 0 = no remote fault ro 0 5.12:11 reserved ro 0 5.10 pause operation 1 = pause oper ation is supported by remote mac, 0 = pause operation is not supported by remote mac ro 0 5.9 100base-t4 1 = t4 able, 0 = no t4 ability. this phy does not support t4 ability. ro 0 5.8 100base-tx full duplex 1 = tx with full duplex, 0 = no tx full duplex ability ro 0 5.7 100base-tx 1 = tx able, 0 = no tx ability ro 0 5.6 10base-t full duplex 1 = 10mbps with full duplex 0 = no 10mbps with full duplex ability ro 0 5.5 10base-t 1 = 10mbps able, 0 = no 10mbps ability ro 0 5.4:0 selector field [00001] = ieee 802.3 ro 00001 table 5.34 register 4 - auto negotiation advertisement (continued) address name description mode default
15kv esd protected mii/rmii 10/100 ethernet transceiver with hp auto-mdix support and flexpwr ? technology in a small footprint datasheet smsc lan8700/lan8700i 45 revision 2.3 (04-12-11) datasheet table 5.36 register 6 - auto negotiation expansion address name descript ion mode default 6.15:5 reserved ro 0 6.4 parallel detection fault 1 = fault detected by parallel detection logic 0 = no fault detected by parallel detection logic ro/ lh 0 6.3 link partner next page able 1 = link partner has next page ability 0 = link partner does not have next page ability ro 0 6.2 next page able 1 = local device has next page ability 0 = local device does not have next page ability ro 0 6.1 page received 1 = new page received 0 = new page not yet received ro/ lh 0 6.0 link partner auto- negotiation able 1 = link partner has auto-negotiation ability 0 = link partner does not have auto-negotiation ability ro 0 table 5.37 register 16 - silicon revision address name description mode default 16.15:10 reserved ro 0 16.9:6 silicon revision four-bit silicon revision identifier. ro 0001 16.5:0 reserved ro 0 table 5.38 register 17 - mode control/status address name description mode default 17.15:14 reserved write as 0; ignore on read. rw 0 17.13 edpwrdown enable the energy detect power-down mode: 0 = energy detect power-down is disabled 1 = energy detect power-down is enabled rw 0 17.12 reserved write as 0, ignore on read rw 0 17.11 lowsqen the low_squelch signal is equal to lowsqen and edpwrdown. low_squelch = 1 implies a lower threshold (more sensitive). low_squelch = 0 implies a higher threshold (less sensitive). rw 0 17.10 mdprebp management data preamble bypass: 0 ? detect smi packets with preamble 1 ? detect smi packets without preamble rw 0 17.9 farloopback force the module to the far loop back mode, i.e. all the received packets are sent back simultaneously (in 100base-tx only). this bit is only active in rmii mode. in this mode the user needs to supply a 50mhz clock to the phy. this mode works even if mii isolate (0.10) is set. rw 0
15kv esd protected mii/rmii 10/100 ethernet transceiver with hp auto-mdix support and flexpwr ? technology in a small footprint datasheet revision 2.3 (04-12-11) 46 smsc lan8700/lan8700i datasheet note 5.1 the default value of this field is determi ned by the strapping of the col/rmii/crs_dv pin. refer to section 4.6.3, "mii vs. rmii configuration," on page 28 for additional information. 17.8:7 reserved write as 0, ignore on read. rw 00 17.6 altint alternate interrupt mode. 0 = primary interrupt syst em enabled (default). 1 = alternate interr upt system enabled. see section 5.3, "interrupt management," on page 49 . rw 0 17.5:4 reserved write as 0, ignore on read. rw 00 17.3 phyadbp 1 = phy disregards phy address in smi access write. rw 0 17.2 force good link status 0 = normal operation; 1 = force 100tx- link active; note: this bit should be set only during lab testing rw 0 17.1 energyon energyon ? indicates whether energy is detected on the line (see section 5.4.5.2, "energy detect power-down," on page 52 ); it goes to ?0? if no valid energy is detected within 256ms. reset to ?1? by hardware reset, unaffected by sw reset. ro x 17.0 reserved write as 0. ignore on read. rw 0 table 5.39 register 18 - special modes address name description mode default 18.15 reserved write as 0, ignore on read. rw 0 18.14 miimode mii mode : reflects the mode of the digital interface: 0 ? mii interface. 1 ? rmii interface note: when writing to this register, the default value of this bit must always be written back. rw, nasr note 5.1 18.13:8 reserved write as 0, ignore on read. rw, nasr 000000 18.7:5 mode phy mode of operation. refer to section 5.4.9.2, "mode bus ? mode[2:0]," on page 56 for more details. rw, nasr xxx evb8700 default 111 18.4:0 phyad phy address. the phy address is used for the smi address and for the initialization of the cipher (scrambler) key. refer to section 5.4.9.1, "ph ysical address bus - phyad[4:0]," on page 56 for more details. rw, nasr phyad evb8700 default 11111 table 5.38 register 17 - mode control/status (continued) address name description mode default
15kv esd protected mii/rmii 10/100 ethernet transceiver with hp auto-mdix support and flexpwr ? technology in a small footprint datasheet smsc lan8700/lan8700i 47 revision 2.3 (04-12-11) datasheet table 5.40 register 26 - symbol error counter address name description mode default 26.15:0 sym_err_cnt 100base-tx receiver-based error register that increments when an invalid code symbol is received including idle symbols. the counter is incremented only once per packet, even when the received packet contains more than one symbol error. the 16-bit register counts up to 65,536 (2 16 ) and rolls over to 0 if incremented beyond that va lue. this register is cleared on reset, but is not cleared by reading the register. it does not increment in 10base-t mode. ro 0 table 5.41 register 27 - speci al control/status indications address name description mode default 27.15 amdixctrl hp auto-mdix control 0 - auto-mdix enable 1 - auto-mdix disabled (use 27.13 to control channel) rw 0 27.14 reserved reserved rw 0 27.13 ch_select manual channel select 0 - mdi -tx transmits rx receives 1 - mdix -tx receives rx transmits rw 0 27.12 reserved write as 0. ignore on read. rw 0 27:11 sqeoff disable the sqe (signal quality error) test (heartbeat): 0 - sqe test is enabled. 1 - sqe test is disabled. rw, nasr 0 27.10:5 reserved write as 0. ignore on read. rw 000000 27.4 xpol polarity state of the 10base-t: 0 - normal polarity 1 - reversed polarity ro 0 27.3:0 reserved reserved ro xxxxb table 5.42 register 28 - special internal testability controls address name description mode default 28.15:0 reserved do not write to th is register. ignore on read. rw n/a table 5.43 register 29 - interrupt source flags address name description mode default 29.15:8 reserved ignore on read. ro/ lh 0 29.7 int7 1 = energyon generated 0 = not source of interrupt ro/ lh x
15kv esd protected mii/rmii 10/100 ethernet transceiver with hp auto-mdix support and flexpwr ? technology in a small footprint datasheet revision 2.3 (04-12-11) 48 smsc lan8700/lan8700i datasheet 29.6 int6 1 = auto-negotiation complete 0 = not source of interrupt ro/ lh x 29.5 int5 1 = remote fault detected 0 = not source of interrupt ro/ lh x 29.4 int4 1 = link down (link status negated) 0 = not source of interrupt ro/ lh x 29.3 int3 1 = auto-negotiation lp acknowledge 0 = not source of interrupt ro/ lh x 29.2 int2 1 = parallel detection fault 0 = not source of interrupt ro/ lh x 29.1 int1 1 = auto-negotiation page received 0 = not source of interrupt ro/ lh x 29.0 reserved ignore on read. ro/ lh 0 table 5.44 register 30 - interrupt mask address name description mode default 30.15:8 reserved write as 0; ignore on read. ro 0 30.7:1 mask bits 1 = interrupt source is enabled 0 = interrupt source is masked rw 0 30.0 reserved write as 0; ignore on read ro 0 table 5.45 register 31 - phy special control/status address name description mode default 31.15:13 reserved write as 0, ignore on read. rw 0 31.12 autodone auto-negotiation done indication: 0 = auto-negotiation is not done or disabled (or not active) 1 = auto-negotiation is done note: this is a duplicate of register 1.5, however reads to register 31 do not clear status bits. ro 0 31.11:10 reserved write as 0, ignore on read. rw xx 31.9:7 reserved write as 0, ignore on read. rw 0 31.6 enable 4b5b 0 = bypass encoder/decoder. 1 = enable 4b5b encoding/decoding. mac interface must be configured in mii mode. rw 1 31.5 reserved write as 0, ignore on read. rw 0 table 5.43 register 29 - interrupt source flags (continued) address name description mode default
15kv esd protected mii/rmii 10/100 ethernet transceiver with hp auto-mdix support and flexpwr ? technology in a small footprint datasheet smsc lan8700/lan8700i 49 revision 2.3 (04-12-11) datasheet 5.3 interrupt management the management interface supports an interrupt cap ability that is not a pa rt of the ieee 802.3 specification. it generat es an active low asynchronous interr upt signal on the nint output whenever certain events are detected as setup by the interrupt mask register 30. the interrupt system on the smsc lan8700/8700i has two modes, a primary interrupt mode and an alternative interrupt mode. both systems will assert the nint pin low when the corresponding mask bit is set, the difference is how they de -assert the output interrupt signal nint. the primary interrupt mode is the default interrupt mode after a power-u p or hard reset, the alternative interrupt mode would need to be setup again after a power-up or hard reset. 5.3.1 primary interrupt system the primary interrupt system is the default interru pt mode, (bit 17.6 = ?0?). the primary interrupt system is always selected after power-up or hard reset. to set an interrupt, set the corresponding mask bit in the interrupt mask register 30 (see ta b l e 5 . 4 6 ). then when the event to assert nint is true, the nint output will be asserted. when the corresponding event to de-assert ni nt is true, then the nint will be de-asserted. 31.4:2 speed indication hcdspeed value: [001]=10mbps half-duplex [101]=10mbps full-duplex [010]=100base-tx half-duplex [110]=100base-tx full-duplex ro xxx 31.1 reserved write as 0; ignore on read rw 0 31.0 scramble disable 0 = enable data scrambling 1 = disable data scrambling, rw 0 table 5.46 interrupt management table mask interrupt source flag interrupt source event to assert nint event to de-assert nint 30.7 29.7 energyon 17.1 energyon rising 17.1 a falling 17.1 or reading register 29 30.6 29.6 auto-negotiation complete 1.5 auto-negotiate complete rising 1.5 falling 1.5 or reading register 29 table 5.45 register 31 - phy special control/status (continued) address name description mode default
15kv esd protected mii/rmii 10/100 ethernet transceiver with hp auto-mdix support and flexpwr ? technology in a small footprint datasheet revision 2.3 (04-12-11) 50 smsc lan8700/lan8700i datasheet note: the energyon bit 17.1 is defaulted to a ?1? at the start of the signal acquisition process, therefore the interrupt source fl ag 29.7 will also read as a ?1? at power-up. if no signal is present, then both 17.1 and 29.7 will clear within a few milliseconds. 5.3.2 alternate interrupt system the alternative method is enabled by writing a ?1? to 17.6 (altint). to set an interrupt, set the corresponding bi t of the in the mask register 30, (see ta b l e 5 . 4 7 ). to clear an interrupt, either clear the correspondin g bit in the mask register (30), this will de-assert the nint output, or clear the interrupt source, an d write a ?1? to the corresponding interrupt source flag. writing a ?1? to the interrupt source flag will cause the state machine to check the interrupt source to determine if the interrupt source flag should clear or stay as a ?1?. if the condition to de- assert is true, then the interrupt source flag is cleared, and the nint is also de-asserted. if the condition to de-assert is false, then the interrupt source flag remains set, and the nint remains asserted. for example 30.7 is set to ?1? to enable the en ergyon interrupt. after a cable is plugged in, energyon (17.1) goes active and nint will be asserted low. 30.5 29.5 remote fault detected 1.4 remote fault rising 1.4 falling 1.4, or reading register 1 or reading register 29 30.4 29.4 link down 1.2 link status falling 1.2 reading register 1 or reading register 29 30.3 29.3 auto-negotiation lp acknowledge 5.14 acknowledge rising 5.14 falling 5.14 or read register 29 30.2 29.2 parallel detection fault 6.4 parallel detection fault rising 6.4 falling 6.4 or reading register 6, or reading register 29 or re-auto negotiate or link down 30.1 29.1 auto-negotiation page received 6.1 page received rising 6.1 falling of 6.1 or reading register 6, or reading register 29 re-auto negotiate, or link down. a. if the mask bit is enabled and nint has been de-asserted while energyon is still high, nint will assert for 256 ms, approximately one second after energyon goes low when the cable is unplugged. to prevent an unexpected assertion of nint, the energyon interrupt mask should always be cleared as part of the energyon interrupt service routine. table 5.46 interrupt management table (continued) mask interrupt source flag interrupt source event to assert nint event to de-assert nint
15kv esd protected mii/rmii 10/100 ethernet transceiver with hp auto-mdix support and flexpwr ? technology in a small footprint datasheet smsc lan8700/lan8700i 51 revision 2.3 (04-12-11) datasheet to de-assert the nint interrupt output, either. 1. clear the energyon bit (17.1), by removing th e cable, then writing a ?1? to register 29.7. or 2. clear the mask bit 30.1 by writing a ?0? to 30.1. note: the energyon bit 17.1 is defaulted to a ?1? at the start of the signal acquisition process, therefore the interrupt source fl ag 29.7 will also read as a ?1? at power-up. if no signal is present, then both 17.1 and 29.7 will clear within a few milliseconds. 5.4 miscellaneous functions 5.4.1 carrier sense the carrier sense is output on crs. crs is a signa l defined by the mii specif ication in th e ieee 802.3u standard. the phy asserts crs based only on receive activity whenever the phy is either in repeater mode or full-duplex mode. otherwise the phy asserts crs based on either transmit or receive activity. the carrier sense logic uses the encoded, unscrambled data to determine carrier activity status. it activates carrier sense with the detection of 2 non-contiguous zeros within any 10 bit span. carrier sense terminates if a span of 10 consecutive ones is detected before a /j/k/ start-of stream delimiter pair. if an ssd pair is detected, carrier sense is asserted until either /t /r/ end?of-stream delimiter pair or a pair of idle symbols is detected. carrier is negated after the /t/ symbol or the first idle. if /t/ is not followed by /r/, then carrier is maintain ed. carrier is treated similarly for idle followed by some non-idle symbol. 5.4.2 collision detect a collision is the occurrence of simultaneous transmit and receive operations. the col output is asserted to indicate that a collision has been detected. col remains active for the duration of the collision. col is changed asynchronously to bo th rx_clk and tx_clk. the col output becomes inactive during full duplex mode. col may be tested by setting register 0, bit 7 high. th is enables the collision test. col will be asserted within 512 bit times of tx_en rising and will be de-asserted within 4 bit times of tx_en falling. in 10m mode, col pulses for approximately 10 bit times (1us), 2us after each transmitted packet (de- assertion of tx_en). this is the signal quality e rror (sqe) signal and indicates that the transmission was successful. the user can disable this pulse by setting bit 11 in register 27. table 5.47 alternative interru pt system management table mask interrupt source flag interrupt source event to assert nint condition to de-assert. bit to clear nint 30.7 29.7 energyon 17.1 energyon rising 17.1 17.1 low 29.7 30.6 29.6 auto-negotiation complete 1.5 auto-negotiate complete rising 1.5 1.5 low 29.6 30.5 29.5 remote fault detected 1.4 remote fault rising 1.4 1.4 low 29.5 30.4 29.4 link down 1.2 link status falling 1.2 1.2 high 29.4 30.3 29.3 auto-negotiation lp acknowledge 5.14 acknowledge rising 5.14 5.14 low 29.3 30.2 29.2 parallel detection fault 6.4 parallel detection fault rising 6.4 6.4 low 29.2 30.1 29.1 auto-negotiation page received 6.1 page received rising 6.1 6.1 low 29.1
15kv esd protected mii/rmii 10/100 ethernet transceiver with hp auto-mdix support and flexpwr ? technology in a small footprint datasheet revision 2.3 (04-12-11) 52 smsc lan8700/lan8700i datasheet 5.4.3 isolate mode the phy data paths may be electrically isolated from the mii by setting register 0, bit 10 to a logic one. in isolation mode, the phy does not respond to the txd, tx_en and tx_er inputs. the phy still responds to management transactions. isolation provides a means for multiple phys to be connected to the same mii without contention occurring. the phy is not isolated on power-up (bit 0:10 = 0). 5.4.4 link integrity test the lan8700/lan8700i performs the link integrity test as outlined in the ieee 802.3u (clause 24-15) link monitor state diagram. the link status is multiplexed with the 10mbps link status to form the reportable link status bit in serial management register 1, and is driven to the link led. the dsp indicates a valid mlt-3 waveform present on the rxp and rxn signals as defined by the ansi x3.263 tp-pmd standard, to the link monitor state-machine, using internal signal called data_valid. when data_valid is asserted the control logic moves into a link-ready state, and waits for an enable from the auto negotiation block. when received, the link-up state is entered, and the transmit and receive l ogic blocks become active. should auto negotiatio n be disabled, the link integrity logic moves immediately to the link-u p state, when the data_valid is asserted. note that to allow the line to stabilize, the li nk integrity logic will wait a minimum of 330 sec from the time data_valid is asserted until the link-ready state is entered. should the data_valid input be negated at any time, this logic will immediately negate the link signal and enter the link-down state. when the 10/100 digital block is in 10base-t mode, t he link status is from the 10base-t receiver logic. 5.4.5 power-down modes there are 2 power-down modes for the phy: 5.4.5.1 general power-down this power-down is controlled by register 0, bi t 11. in this mode the entire phy, except the management interface, is powered-down and stays in that condition as long as bit 0.11 is high. when bit 0.11 is cleared, the phy powers up and is automatically reset. 5.4.5.2 energy detect power-down this power-down mode is activated by setting bit 17.13 to 1. in this mode when no energy is present on the line the phy is powered down, except for the management interface, the squelch circuit and the energyon logic. the energyon logic is used to detect the presence of valid energy from 100base-tx, 10base-t, or auto-negotiation signals in this mode, when the energyon signal is low, the phy is powered-down, and nothing is transmitted. when energy is received - link pulses or packets - the energyon signal goes high, and the phy powers-up. it automatically resets itself into the state it had prior to power-down, and asserts the nint interrupt if the energyon interrupt is enabled. the first and possibly the second packet to activate energyon may be lost. when 17.13 is low, energy detect power-down is disabled.
15kv esd protected mii/rmii 10/100 ethernet transceiver with hp auto-mdix support and flexpwr ? technology in a small footprint datasheet smsc lan8700/lan8700i 53 revision 2.3 (04-12-11) datasheet 5.4.6 reset the phy has 3 reset sources: hardware reset (hwrst) : connected to the nrst input. at pow er up, nrst must not go high until after the vddio and vdd_core supp lies are stable, as shown in figure 5.1 . to initiate a hardware reset, nrst must be held low for at least 100 us to ensure that the phy is properly reset, as shown in figure 6.10 . during a hardware reset, an external clock must be supplied to the clkin signal. software (sw) reset : activated by writing register 0, bit 15 high. this signal is self- clearing. after the register-write, internal logic extends the reset by 256s to allow pll-stabilization before releasing the logic from reset. the ieee 802.3u standard, clause 22 (22.2.4.1.1) states that the reset process should be completed within 0.5s from the setting of this bit. power-down reset : automatically activated when the phy comes out of power-down mode. the internal power-down reset is extended by 256s af ter exiting the power-down mode to allow the plls to stabilize before the logic is released from reset. these 3 reset sources are combined together in the digi tal block to create the internal ?general reset?, sysrst, which is an asynchronous reset and is active high. this sysrst directly drives the pcs, dsp and mii blocks. it is also input to the central bias block in order to generate a short reset for the plls. the smi mechanism and registers are reset only by the hardware and software resets. during power- down, the smi registers are not reset. note that so me smi register bits are not cleared by software reset ? these are marked ?nasr? in the register tables. for the first 16us after coming out of reset, the mii wil l run at 2.5 mhz. after t hat it will switch to 25 mhz if auto-negotiation is enabled. figure 5.1 reset timing diagram vdd_core starts nrst released 0v 3.3v 1.8v vdd33 starts
15kv esd protected mii/rmii 10/100 ethernet transceiver with hp auto-mdix support and flexpwr ? technology in a small footprint datasheet revision 2.3 (04-12-11) 54 smsc lan8700/lan8700i datasheet 5.4.7 led description the phy provides four led signals. these prov ide a convenient means to determine the mode of operation of the phy. all led signals are either active high or active low. the four led signals can be either active-high or active-low. polarity depends upon the phy address latched in on reset. the lan8700/lan8700i senses each phy address bit and changes the polarity of the led signal accordingly. if the address bit is set as level ?1?, the led polarity will be set to an active- low. if the address bit is set as level ?0?, the led polarity will be set to an active-high. the activity led output is driven active when crs is active (high). when crs becomes inactive, the activity led output is extended by 128ms. the link led output is driven active whenever the phy detects a valid link. the use of the 10mbps or 100mbps link test status is determined by the co ndition of the internally determined speed selection. the speed100 led outp ut is driven active when the operating s peed is 100mbit/s or during auto- negotiation. this led will go inactive when the oper ating speed is 10mbit/s or during line isolation (register 31 bit 5). the full-duplex led output is driven active lo w when the link is operating in full-duplex mode. 5.4.8 loopback operation the lan8700/lan8700i may be configured for near-end loopback and far loopback. 5.4.8.1 near-end loopback near-end loopback is a mode that sends the digital tr ansmit data back out the receive data signals for testing purposes as indicated by the blue arrows in figure 5.2 .the near-end loopback mode is enabled by setting bit register 0 bit 14 to logic one. a large percentage of the digital circuitry is operational near-end loopback mode, because data is routed through the pcs and pma layers into the pm d sublayer before it is looped back. the col signal will be inactive in this mode, unless collision test (bit 0.7) is active. th e transmitters are powered down, regardless of the state of txen. figure 5.2 near-end loopback block diagram smsc ethernet transceiver 10/100 ethernet mac cat-5 xfmr digital rxd txd analog rx tx x x
15kv esd protected mii/rmii 10/100 ethernet transceiver with hp auto-mdix support and flexpwr ? technology in a small footprint datasheet smsc lan8700/lan8700i 55 revision 2.3 (04-12-11) datasheet 5.4.8.2 far loopback far loopback is a special test mode for mdi (analog ) loopback as indicated by the blue arrows in figure 5.3 . the far loopback mode is enabled by setting bit register 17 bit 9 to logic one. in this mode, data that is received from the link partner on the mdi is looped back out to the link partner. the digital interface signals on the local mac interface are isolated. note: this special test mode is only av ailable when operating in rmii mode. 5.4.8.3 connector loopback the lan8700/lan8700i maintains reliable transmissi on over very short cables, and can be tested in a connector loopback as shown in figure 5.4 . an rj45 loopback cable can be used to route the transmit signals an the output of the transformer back to the receiver inputs, and this loopback will work at both 10 and 100. figure 5.3 far loopback block diagram figure 5.4 connector loopback block diagram far-end system smsc ethernet transceiver 10/100 ethernet mac cat-5 xfmr digital rxd txd analog rx tx link partner x x smsc ethernet transceiver 10/100 ethernet mac xfmr digital rxd txd analog rx tx 1 2 3 4 5 6 7 8 rj45 loopback cable. created by connecting pin 1 to pin 3 and connecting pin 2 to pin 6.
15kv esd protected mii/rmii 10/100 ethernet transceiver with hp auto-mdix support and flexpwr ? technology in a small footprint datasheet revision 2.3 (04-12-11) 56 smsc lan8700/lan8700i datasheet 5.4.9 configuration signals the phy has 11 configuration signals whose inputs s hould be driven continuously, either by external logic or external pull-up/pull-down resistors. 5.4.9.1 physical address bus - phyad[4:0] the phyad[4:0] signals are driven high or low to give each phy a unique address. this address is latched into an internal register at end of hardware reset. in a multi-phy application (such as a repeater), the controller is able to manage each phy via the unique address. each phy checks each management data frame for a matching address in the relevant bits. when a match is recognized, the phy responds to that particular frame. the phy add ress is also used to seed the scrambler. in a multi- phy application, this ensures t hat the scramblers are out of synchronization and disperses the electromagnetic radiation ac ross the frequency spectrum. 5.4.9.2 mode bus ? mode[2:0] the mode[2:0] bus controls the configuration of the 10/100 digital block. when the nrst pin is deasserted, the register bit values are loaded according to the mode[2:0] pins. the 10/100 digital block is then configured by the register bit values. when a soft reset occurs (bit 0.15) as described in table 5.30 , the configuration of the 10/100 digital block is controlled by the register bit values, and the mode[2:0] pins have no affect. table 5.48 mode[2:0] bus mode[2:0] mode definitions default register bit values register 0 register 4 [13,12,10,8] [8,7,6,5] 000 10base-t half duplex. auto-negotiation disabled. 0000 n/a 001 10base-t full duplex. auto-negotiation disabled. 0001 n/a 010 100base-tx half duplex. auto-negotiation disabled. crs is active during transmit & receive. 1000 n/a 011 100base-tx full duplex. auto-negotiation disabled. crs is active during receive. 1001 n/a 100 100base-tx half duplex is advertised. auto- negotiation enabled. crs is active during transmit & receive. 1100 0100 101 repeater mode. auto -negotiation enabled. 100base-tx half duplex is advertised. crs is active during receive. 1100 0100 110 power down mode. in this mode the phy will wake-up in power-down mode. the phy cannot be used when the mode[2:0] bits are set to this mode. to exit this mode, the mode bits in register 18.7:5 (see ta b l e 5 . 3 9 ) must be configured to some other value and a soft reset must be issued. n/a n/a 111 all capable. auto-negotiation enabled. x10x 1111
15kv esd protected mii/rmii 10/100 ethernet transceiver with hp auto-mdix support and flexpwr ? technology in a small footprint datasheet smsc lan8700/lan8700i 57 revision 2.3 (04-12-11) datasheet chapter 6 ac electrical characteristics the timing diagrams and limits in this section define the requirements placed on the external signals of the phy. 6.1 serial management interface (smi) timing the serial management interface is used fo r status and control as described in section 4.13 . figure 6.1 smi timing diagram table 6.1 smi timing values parameter description min typ max units notes t1.1 mdc minimum cycle time 400 ns t1.2 mdc to mdio (read from phy) delay 0 300 ns t1.3 mdio (write to phy) to mdc setup 10 ns t1.4 mdio (write to phy) to mdc hold 10 ns clock - mdc data out - mdio t 1.2 valid data (read from phy) t 1.1 t 1.3 t 1.4 data in - mdio valid data (write to phy)
15kv esd protected mii/rmii 10/100 ethernet transceiver with hp auto-mdix support and flexpwr ? technology in a small footprint datasheet revision 2.3 (04-12-11) 58 smsc lan8700/lan8700i datasheet 6.2 mii 10/100base-tx/rx timings 6.2.1 mii 100base- t tx/rx timings 6.2.1.1 100m mii receive timing figure 6.2 100m mii receive timing diagram table 6.2 100m mii receive timing values parameter description min typ max units notes t2.1 receive signals setup to rx_clk rising 10 ns t2.2 receive signals hold from rx_clk rising 10 ns rx_clk frequency 25 mhz rx_clk duty-cycle 40 % clock out - rx_clk data out - rxd[3:0] t 2.1 rx_dv rx_er t 2.2 valid data
15kv esd protected mii/rmii 10/100 ethernet transceiver with hp auto-mdix support and flexpwr ? technology in a small footprint datasheet smsc lan8700/lan8700i 59 revision 2.3 (04-12-11) datasheet 6.2.1.2 100m mii transmit timing figure 6.3 100m mii transmit timing diagram table 6.3 100m mii transmit timing values parameter description min typ max units notes t3.1 transmit signals required setup to tx_clk rising 12 ns transmit signals required hold after tx_clk rising 0ns tx_clk frequency 25 mhz tx_clk duty-cycle 40 % clock out - tx_clk data out - txd[3:0] t 3.1 tx_en tx_er valid data
15kv esd protected mii/rmii 10/100 ethernet transceiver with hp auto-mdix support and flexpwr ? technology in a small footprint datasheet revision 2.3 (04-12-11) 60 smsc lan8700/lan8700i datasheet 6.2.2 mii 10base-t tx/rx timings 6.2.2.1 10m mii receive timing figure 6.4 10m mii receive timing diagram table 6.4 10m mii receive timing values parameter description min typ max units notes t4.1 receive signals setup to rx_clk rising 10 ns t4.2 receive signals hold from rx_clk rising 10 ns rx_clk frequency 2.5 mhz rx_clk duty-cycle 40 % clock out - rx_clk data out - rxd[3:0] t 4.1 rx_dv t 4.2 valid data
15kv esd protected mii/rmii 10/100 ethernet transceiver with hp auto-mdix support and flexpwr ? technology in a small footprint datasheet smsc lan8700/lan8700i 61 revision 2.3 (04-12-11) datasheet 6.2.2.2 10m mii transmit timing figure 6.5 10m mii transmit timing diagrams table 6.5 10m mii transmit timing values parameter description min typ max units notes t5.1 transmit signals required setup to tx_clk rising 12 ns transmit signals required hold after tx_clk rising 0ns tx_clk frequency 2.5 mhz tx_clk duty-cycle 50 % clock out - tx_clk data out - txd[3:0] t 5.1 tx_en valid data
15kv esd protected mii/rmii 10/100 ethernet transceiver with hp auto-mdix support and flexpwr ? technology in a small footprint datasheet revision 2.3 (04-12-11) 62 smsc lan8700/lan8700i datasheet 6.3 rmii 10/100base-tx/rx timings 6.3.1 rmii 100bas e-t tx/rx timings 6.3.1.1 100m rmii receive timing figure 6.6 100m rmii re ceive timing diagram table 6.6 100m rmii receive timing values parameter description min typ max units notes t6.1 output delay from rising edge of clkin to receive signals output valid 210ns clkin frequency 50 mhz clock in - clkin data out - rxd[1:0] crs_dv valid data t 6.1
15kv esd protected mii/rmii 10/100 ethernet transceiver with hp auto-mdix support and flexpwr ? technology in a small footprint datasheet smsc lan8700/lan8700i 63 revision 2.3 (04-12-11) datasheet 6.3.1.2 100m rmii transmit timing figure 6.7 100m rmii tr ansmit timing diagram table 6.7 100m rmii transmit timing values parameter description min typ max units notes t8.1 transmit signals required setup to rising edge of clkin 2ns t8.2 transmit signals required hold after rising edge of ref_clk 1.5 ns clkin frequency 50 mhz clock in - clkin data out - txd[1:0] t 8.1 tx_en t 8.2 valid data
15kv esd protected mii/rmii 10/100 ethernet transceiver with hp auto-mdix support and flexpwr ? technology in a small footprint datasheet revision 2.3 (04-12-11) 64 smsc lan8700/lan8700i datasheet 6.3.2 rmii 10base-t tx/rx timings 6.3.2.1 10m rmii receive timing figure 6.8 10m rmii receive timing diagram table 6.8 10m rmii receive timing values parameter description min typ max units notes t9.1 output delay from rising edge of clkin to receive signals output valid 210ns clkin frequency 50 mhz clock in - clkin data out - rxd[1:0] crs_dv valid data t 9.1
15kv esd protected mii/rmii 10/100 ethernet transceiver with hp auto-mdix support and flexpwr ? technology in a small footprint datasheet smsc lan8700/lan8700i 65 revision 2.3 (04-12-11) datasheet 6.3.2.2 10m rmii transmit timing figure 6.9 10m rmii transmit timing diagram table 6.9 10m rmii transmit timing values parameter description min typ max units notes t10.1 transmit signals required setup to rising edge of clkin 4ns t10.2 transmit signals required hold after rising edge of ref_clk 2ns clkin frequency 50 mhz clock in - clkin data out - txd[1:0] t 10.1 tx_en t 10.2 valid data
15kv esd protected mii/rmii 10/100 ethernet transceiver with hp auto-mdix support and flexpwr ? technology in a small footprint datasheet revision 2.3 (04-12-11) 66 smsc lan8700/lan8700i datasheet 6.4 rmii clkin timing 6.5 reset timing table 6.10 rmii clkin (ref_clk)timing values parameter description min typ max units notes clkin frequency 50 mhz clkin frequency drift 50 ppm clkin duty cycle 40 60 % clkin jitter 150 psec p-p ? not rms figure 6.10 reset timing diagram table 6.11 reset timing values parameter description min typ max units notes t11.1 reset pulse width 100 us t11.2 configuration input setup to nrst rising 200 ns t11.3 configuration input hold after nrst rising 2ns t11.4 output drive after nrst rising 3 800 ns 20 clock cycles for 25 mhz clock or 40 clock cycles for 50mhz clock nrst configuration signals t 11.1 t 11.4 output drive t 11.2 t 11.3
15kv esd protected mii/rmii 10/100 ethernet transceiver with hp auto-mdix support and flexpwr ? technology in a small footprint datasheet smsc lan8700/lan8700i 67 revision 2.3 (04-12-11) datasheet 6.6 clock circuit lan8700/lan8700i can accept either a 25mhz cr ystal or a 25mhz single-ended clock oscillator (50ppm) input for operation in mii mode. if the single-ended clock oscillator method is implemented, xtal2 should be left unconnected and xtal1/clki n should be driven with a nominal 0-3.3v clock signal. the user is required to supply a 50mhz single-ended clock for rmii operation. the input clock duty cycle is 40% minimum, 50% typical and 60% maximum. see ta b l e 6 . 1 2 for the recommended crystal specifications. note 6.1 the maximum allowable values for frequency tolerance and frequency stability are application dependant. since any particular appl ication must meet the ieee 50 ppm total ppm budget, the combination of these two values must be approximately 45 ppm (allowing for aging). note 6.2 frequency deviation over time is also referred to as aging. note 6.3 the total deviation for the transmitter clock frequency is specified by ieee 802.3u as 100 ppm. note 6.4 0 o c for commercial version, -40 o c for industrial version. note 6.5 +70 o c for commercial version, +85 o c for industrial version. this number includes the pad, the bond wire and t he lead frame. pcb capacitance is not included in this value. the xtal1/clkin pin, xtal2 pin and pc b capacitance values are required to accurately calculate the value of the two external load capaci tors. the total load capacitance must be equivalent to what the crystal expects to see in the circuit so that the crystal oscillator will operate at 25.000 mhz. table 6.12 lan8700/lan8700i crystal specifications parameter symbol min nom max units notes crystal cut at, typ crystal oscillation mode fundamental mode crystal calibration mode parallel resonant mode frequency f fund - 25.000 - mhz frequency tolerance @ 25 o cf tol - - 50 ppm note 6.1 frequency stability over temp f temp - - 50 ppm note 6.1 frequency deviation over time f age - +/-3 to 5 - ppm note 6.2 total allowable ppm budget - - 50 ppm note 6.3 shunt capacitance c o -7 typ-pf load capacitance c l - 20 typ - pf drive level p w 0.5 - - mw equivalent series resistance r 1 --30ohm operating temperature range note 6.4 - note 6.5 o c lan8700/lan8700i xtal1/clkin pin capacitance -3 typ-pf lan8700/lan8700i xtal2 pin capacitance -3 typ-pf
15kv esd protected mii/rmii 10/100 ethernet transceiver with hp auto-mdix support and flexpwr ? technology in a small footprint datasheet revision 2.3 (04-12-11) 68 smsc lan8700/lan8700i datasheet chapter 7 dc electrical characteristics 7.1 dc characteristics 7.1.1 maximum guaranteed ratings stresses beyond those listed in may cause permanent damage to the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 7.1.1.1 human body model (hbm) performance hbm testing verifies the ability to withstand the esd strikes like those that occur during handling and manufacturing, and is done without power applied to the ic. to pass the test, the device must have no change in operation or performance due to the ev ent. all pins on the lan8700 provide 8kv hbm protection. table 7.1 maximum conditions parameter conditions min typ max units comment vdd33,vddio power pins to all other pins. -0.5 +3.6 v digital io to vss ground -0.5 +3.6 v table 7.5, ?mii bus interface signals,? on page 71 vss vss to all other pins -0.5 +4.0 v operating temperature lan8700-aezg 0 +70 c commercial temperature components. operating temperature lan8700i-aezg -40 +85 c industrial temperature components. storage temperature -55 +150 c table 7.2 esd and latch-up performance parameter conditions min typ max units comments esd performance all pins human body model 8 kv device system en/iec61000-4-2 contact discharge 8 kv 3rd party system test system en/iec61000-4-2 air-gap discharge 15 kv 3rd party system test latch-up performance all pins eia/jesd 78, class ii 150 ma
15kv esd protected mii/rmii 10/100 ethernet transceiver with hp auto-mdix support and flexpwr ? technology in a small footprint datasheet smsc lan8700/lan8700i 69 revision 2.3 (04-12-11) datasheet 7.1.1.2 ien/iec61000-4-2 performance the en/iec61000-4-2 esd specificat ion is an international standard that addresses system-level immunity to esd strikes while the end equipment is operational. in contrast, the hbm esd tests are performed at the device level with the device powered down. smsc contracts with independent laboratories to test the lan8700 to en/iec61000-4-2 in a working system. reports are available upon request. please contact your smsc repr esentative, and request information on 3rd party esd test results. the repor ts show that systems designed with the lan8700 can safely dissipate 15kv air discharges and 8kv contact discharges per the en/iec61000-4-2 specification without additional board level protection. in addition to defining the esd tests, en/iec61000-4-2 also categorizes the impact to equipment operation when the strike occurs (esd result classification). the lan8700 maintains an esd result classification 1 or 2 when subjected to an en/iec61000-4-2 (level 4) esd strike. both air discharge and contact discharge test techni ques for applying stress conditions are defined by the en/iec61000-4-2 esd document. air discharge to perform this test, a charged electrode is moved close to the system being tested until a spark is generated. this test is difficult to reproduce because the discharge is influenced by such factors as humidity, the speed of approach of the electrode, and constr uction of the test equipment. contact discharge the uncharged electrode first contacts the pin to pr epare this test, and then the probe tip is energized. this yields more repeatable results, and is the pr eferred test method. the independent test laboratories contracted by smsc provide test result s for both types of discharge methods. 7.1.2 operating conditions 7.1.3 power consumption 7.1.3.1 power consumption device only power measurements taken over the operating conditions specified. see section 5.4.5 for a description of the power down modes. table 7.3 recommended operating conditions parameter conditions min typ max units comment vdd33 vdd33 to vss 3.0 3.3 3.6 v input voltage on digital pins 0.0 vddio v voltage on analog i/o pins (rxp, rxn) 0.0 +3.6v v ambient temperature t a lan8700-aezg 0 70 c for commercial temperature t a lan8700i-aezg -40 +85 c for industrial temperature
15kv esd protected mii/rmii 10/100 ethernet transceiver with hp auto-mdix support and flexpwr ? technology in a small footprint datasheet revision 2.3 (04-12-11) 70 smsc lan8700/lan8700i datasheet note: the current at vdd_core is either supplied by the internal regulator from current entering at vdd33, or from an external 1.8v supply when the internal regulator is disabled. note 7.1 this is calculated with full flexpwr features activated: vddio = 1.8v and internal regulator disabled. note 7.2 current measurements do not include power applied to the magnetics or the optional external leds. current measurements taken with vddio = +3.3v, unless otherwise indicated. table 7.4 power consumption device only power pin group vdda3.3 power pins(ma) vdd_core power pin(ma) vddio power pin(ma) total current (ma) total power (mw) 100base-t /w traffic max 35.6 41.3 4.7 81.6 269.28 typical 33.3 37.4 4.1 74.8 246.84 min 31.3 33.4 1.3 66 165.75 note 7.1 10base-t /w traffic max 15.6 22.3 1.1 39 128.7 typical 15.3 20.8 0.9 37 122.1 min 14.9 19.1 0.1 34.1 83.88 note 7.1 energy detect power down max 10.5 3.3 0.5 13.85 45.7 typical 9.9 2.7 0.4 13.0 42.9 min 9.8 2.3 0.3 12.4 37.02 note 7.1 general power down max 0.21 2.92 0.39 3.52 11.62 typical 0.124 2.6 0.345 3.07 10.131 min 0.038 2.1 0.3 2.44 4.4454 note 7.1
15kv esd protected mii/rmii 10/100 ethernet transceiver with hp auto-mdix support and flexpwr ? technology in a small footprint datasheet smsc lan8700/lan8700i 71 revision 2.3 (04-12-11) datasheet 7.1.4 dc characteristics - i nput and output buffers table 7.5 mii bus interface signals name v ih (v) v il (v) i oh i ol v ol (v) v oh (v) txd0 0.68 * vddio 0.4 * vddio txd1 0.68 * vddio 0.4 * vddio txd2 0.68 * vddio 0.4 * vddio txd3 0.68 * vddio 0.4 * vddio tx_en 0.68 * vddio 0.4 * vddio tx_clk -8 ma +8 ma +0.4 vddio ? +0.4 rxd0/mode0 -8 ma +8 ma +0.4 vddio ? +0.4 rxd1/mode1 -8 ma +8 ma +0.4 vddio ? +0.4 rxd2/mode2 -8 ma +8 ma +0.4 vddio ? +0.4 rxd3/nintsel -8 ma +8 ma +0.4 vddio ? +0.4 rx_er/rxd4 -8 ma +8 ma +0.4 vddio ? +0.4 rx_dv -8 ma +8 ma +0.4 vddio ? +0.4 rx_clk/regoff -8 ma +8 ma +0.4 vddio ? +0.4 crs/phyad4 -8 ma +8 ma +0.4 vddio ? +0.4 col/rmii/crs_dv -8 ma +8 ma +0.4 vddio ? +0.4 mdc 0.68 * vddio 0.4 * vddio mdio 0.68 * vddio 0.4 * vddi o -8 ma +8 ma +0.4 vddio ? +0.4 nint/tx_er/txd4 0 .68 * vddio 0.4 * vddio -8 ma +8 ma +0.4 3.6
15kv esd protected mii/rmii 10/100 ethernet transceiver with hp auto-mdix support and flexpwr ? technology in a small footprint datasheet revision 2.3 (04-12-11) 72 smsc lan8700/lan8700i datasheet table 7.6 lan interface signals name v ih v il i oh i ol v ol v oh txp see table 7.12, ?100base-tx transceiver characteristics,? on page 74 and ta b l e 7 . 1 3 , ?10base-t transceiver characteristics,? on page 74 . txn rxp rxn table 7.7 led signals name v ih (v) v il (v) i oh i ol v ol (v) v oh (v) speed100/phyad0 0.68 * vddio 0.4 * vd dio -12 ma +12 ma +0.4 vddio ? +0.4 link/phyad1 0.68 * vddio 0.4 * vddio -12 ma +12 ma +0.4 vddio ? +0.4 activity/phyad2 0.68 * vddio 0.4 * vddio -12 ma +12 ma +0.4 vddio ? +0.4 fduplex/phyad3 0.68 * vddio 0.4 * vddio -12 ma +12 ma +0.4 vddio ? +0.4 table 7.8 configuration inputs name v ih (v) v il (v) i oh i ol v ol (v) v oh (v) speed100/phyad0 0.68 * vddio 0.4 * vd dio -12 ma +12 ma +0.4 vddio ? +0.4 link/phyad1 0.68 * vddio 0.4 * vddio -12 ma +12 ma +0.4 vddio ? +0.4 activity/phyad2 0.68 * vddio 0.4 * vddio -12 ma +12 ma +0.4 vddio ? +0.4 fduplex/phyad3 0.68 * vddio 0.4 * vddio -12 ma +12 ma +0.4 vddio ? +0.4 crs/phyad4 0.68 * vddio 0.4 * vddio -8 ma +8 ma +0.4 vddio ? +0.4 rxd0/mode0 0.68 * vddio 0.4 * vddio rxd1/mode1 0.68 * vddio 0.4 * vddio rxd2/mode2 0.68 * vddio 0.4 * vddio rx_clk/regoff 0.68 * vddio 0.4 * vddio col/rmii/crs_dv -8 ma +8 ma +0.4 vddio ? +0.4
15kv esd protected mii/rmii 10/100 ethernet transceiver with hp auto-mdix support and flexpwr ? technology in a small footprint datasheet smsc lan8700/lan8700i 73 revision 2.3 (04-12-11) datasheet note 7.3 these levels apply when a 0-3.3v clock is driven into clkin/xtal1 and xtal2 is floating. the maximum input voltage on xtal1 is vddio + 0.4v. table 7.9 general signals name v ih (v) v il (v) i oh i ol v ol (v) v oh (v) nint/tx_er/txd4 -8 ma +8 ma +0.4 vddio ? +0.4 nrst 0.68 * vddio 0.4 * vddio clkin/xtal1 ( note 7.3 ) +1.40 v 0.4 * vddio xtal2 - - nc table 7.10 analog references name buffer type v ih v il i oh i ol v ol v oh exres1 ai table 7.11 internal pull-up / pull-down configurations name pull-up or pull-down speed100/phyad0 pull-up link/phyad1 pull-up activity/phyad2 pull-up fduplex/phyad3 pull-up crs/phyad4 pull-up rxd0/mode0 pull-up rxd1/mode1 pull-up rxd2/mode2 pull-up rxd3/nintsel pull-up nint/tx_er/txd4 pull-up nrst pull-up col/rmii/crs_dv pull-down mdio pull-down mdc pull-down rx_clk/regoff pull-down rx_er/rxd4 pull-down rx_dv pull-down tx_en pull-down
15kv esd protected mii/rmii 10/100 ethernet transceiver with hp auto-mdix support and flexpwr ? technology in a small footprint datasheet revision 2.3 (04-12-11) 74 smsc lan8700/lan8700i datasheet note: for vddio operation below +2.5v, smsc recommends designs add external strapping resistors in addition the internal strapping resistors to ensure proper strapped operation. note 7.4 measured at the line side of the transformer, line replaced by 100 ( 1%) resistor. note 7.5 offset from 16 ns pulse width at 50% of pulse peak note 7.6 measured differentially. note 7.7 min/max voltages guaranteed as measured with 100 resistive load. table 7.12 100base-tx transceiver characteristics parameter symbol min typ max units notes peak differential output voltage high v pph 950 - 1050 mvpk note 7.4 peak differential output voltage low v ppl -950 - -1050 mvpk note 7.4 signal amplitude symmetry v ss 98 - 102 % note 7.4 signal rise & fall time t rf 3.0 - 5.0 ns note 7.4 rise & fall time symmetry t rfs --0.5ns note 7.4 duty cycle distortion d cd 35 50 65 % note 7.5 overshoot & undershoot v os --5 % jitter 1.4 ns note 7.6 table 7.13 10base-t transceiver characteristics parameter symbol min typ max units notes transmitter peak differential output voltage v out 2.2 2.5 2.8 v note 7.7 receiver differential squelch threshold v ds 300 420 585 mv
15kv esd protected mii/rmii 10/100 ethernet transceiver with hp auto-mdix support and flexpwr ? technology in a small footprint datasheet smsc lan8700/lan8700i 75 revision 2.3 (04-12-11) datasheet chapter 8 application notes 8.1 application diagram note: r5 on the crystal is used to control the cryst al drive strength into the phy clock generator. this resistance can be fine tuned to meet t he requirements of each crystal manufacturer. figure 8.1 simplified application diagram (see section 8.4, "reference designs" ) host system mac (media access controller) mii/rmii rx_clk/regoff nint/tx_er/txd4 mdc crs/phyad4 mdio nrst tx_en vdd_core vdd33 link/phyad1 activity/phyad2 fduplex/phyad3 xtal2 clkin/xtal1 rxd3/nintsel rxd1/mode1 rxd2/mode2 txd3 tx_clk rx_er/rxd4 vddio txd1 txd0 txd2 col/rmii/crs_dv txp rxn exres1 vdda3.3 rxp vdda3.3 1 2 3 4 5 6 7 8 lan8700/lan8700i mii/rmii ethernet phy 36 pin qfn gnd flag 10 11 12 13 14 15 16 24 23 22 21 20 19 32 31 30 29 28 speed100/phyad0 9 rx_dv rxd0/mode0 17 txn 18 27 26 25 36 35 34 33 vddio 4.7uf 0.1uf variable voltage io regulator integrated magnetics and rj45 jack 12.4k 1% 4.7uf 0.1uf r1 r2 vdd3.3 4.7uf 0.1uf vdd3.3 voltage regulator 0.1uf speed100 link activity fullduplex r3 r4 vdda3.3 0.1uf 0.1uf 0.1uf 1 2 3 4 5 6 7 8
15kv esd protected mii/rmii 10/100 ethernet transceiver with hp auto-mdix support and flexpwr ? technology in a small footprint datasheet revision 2.3 (04-12-11) 76 smsc lan8700/lan8700i datasheet 8.2 magnetics selection for a list of magnetics selected to operate with the smsc lan8700, please refer to the application note ?an 8-13 suggested magnetics?. http://www.smsc.com/main/appn otes.html#ethernet%20products 8.3 application notes application examples are given in pdf format on t he smsc lan8700 web site. the link to the web site is shown below. http://www.smsc.com/ma in/catalog/lan8700.html please check the web site periodically for the latest updates. 8.4 reference designs the lan8700 reference designs are available on the smsc lan8700 web site link below. http://www.smsc.com/ma in/catalog/lan8700.html the reference designs are available in four variations: a. mii with +3.3v io b. rmii with +3.3v io c. mii with +1.8v io d. rmii with +1.8v io. 8.5 evaluation board the evb-lan8700 is a a phy evalua tion board (evb) that interfaces a mac controller to the smsc lan8700 ethernet phy through an mii connector, and out to an rj-45 ethernet jack through industrial temperature magnetics for 10/100 connectivity. schematics(*.pdf and *.dsn), bom (bill of materials), user guide, ger ber files and layout board file are all available on the evb web site link below. http://www.smsc.com/ma in/catalog/evblan8700.html the evb-lan8700 is designed to plug into a user 's test system using a 40 pin media independent interface (mii) connector. the mii connector is an amp 40 pin right angle through hole mii connector, pn amp- 174218-2. the mating connector is pn amp 174217-2. features: ? industrial temperature phy and magnetics ? 8 pin soic for user configurable magnetics ? on board led indicators for speed 100 ? full duplex ? rj-45 connector leds for link and activity ? interfaces through 40-pin connector as defined in the mii specification ? powered by 5.0v from the 40-pin mii connector ? standard rj45 connector with led indicators for link and activity ? includes probe points on all mii data and control signals for troubleshooting
15kv esd protected mii/rmii 10/100 ethernet transceiver with hp auto-mdix support and flexpwr ? technology in a small footprint datasheet smsc lan8700/lan8700i 77 revision 2.3 (04-12-11) datasheet ? includes 25mhz crystal for internal phy reference; rx_clk is supplied to the 40-pin connector ? supports user configuration options including phy address selection ? integrated 3.3v regulator applications the evb8700 evaluation board simplifies the process of testing and evaluating an ethernet connection in your application. the lan8700 device is installed on the evb board and all associated circuitry is included, along with all configuration options. the benefits of adding an external mii interface are: ? easier system and software development ? verify mac to phy interface ? support testing of fpga implementations of mac ? assist interoperability test of various networks ? verify mii compliance ? verify performance of hp automdix feature ? verify variable io compliance
15kv esd protected mii/rmii 10/100 ethernet transceiver with hp auto-mdix support and flexpwr ? technology in a small footprint datasheet revision 2.3 (04-12-11) 78 smsc lan8700/lan8700i datasheet chapter 9 package outline, tape and reel figure 9.1 36-pin qfn package outline, 6 x 6 x 0.90 mm body (lead-free) notes: 1. controlling unit: millimeter. 2. dimension b applies to plated terminals and is measured between 0.15mm and 0.30mm from the terminal tip. tolerance on the true position of the terminal is 0.05 mm at maximum material conditions (mmc). 3. details of terminal #1 identifier are optional but must be located within the zone indicated. 4. coplanarity zone applies to exposed pad and terminals. table 9.1 36-pin qfn package parameters min nominal max remarks a 0.80 ~ 1.00 overall package height a1 0 ~ 0.05 standoff a2 0.60 ~ 0.80 mold thickness a3 0.20 ref copper lead-frame substrate d 5.85 ~ 6.15 x overall size d1 5.55 ~ 5.95 x mold cap size d2 3.55 ~ 3.85 x exposed pad size e 5.85 ~ 6.15 y overall size e1 5.55 ~ 5.95 y mold cap size e2 3.55 ~ 3.85 y exposed pad size l 0.35 ~ 0.75 terminal length e 0.50 basic terminal pitch b 0.18 ~ 0.30 terminal width ccc ~ ~ 0.08 coplanarity
15kv esd protected mii/rmii 10/100 ethernet transceiver with hp auto-mdix support and flexpwr ? technology in a small footprint datasheet smsc lan8700/lan8700i 79 revision 2.3 (04-12-11) datasheet figure 9.2 qfn, 6x6 tape & reel
15kv esd protected mii/rmii 10/100 ethernet transceiver with hp auto-mdix support and flexpwr ? technology in a small footprint datasheet revision 2.3 (04-12-11) 80 smsc lan8700/lan8700i datasheet note: standard reel size is 3000 pieces per reel. figure 9.3 reel dimensions
15kv esd protected mii/rmii 10/100 ethernet transceiver with hp auto-mdix support and flexpwr ? technology in a small footprint datasheet smsc lan8700/lan8700i 81 revision 2.3 (04-12-11) datasheet chapter 10 datasheet revision history table 10.1 customer revision history revision level & date section/figure/entry correction rev. 2.3 (04-12-11) section 6.5, "reset timing," on page 66 corrected t11.4 minimum value to 3ns. corrected t11.3 to 2ns. table 5.39, ?register 18 - special modes,? on page 46 ? updated miimode bit description and added note: ?when writing to th is register, the default value of this bit must always be written back.? ? added note regarding default miimode value. section 4.6.3, "mii vs. rmii configuration," on page 28 updated section to remove information about register control of the mii/rmii mode. section 5.4.8.2, "far loopback," on page 55 updated section to remove information about register control of the mii/rmii mode. rev. 2.2 (12-04-09) table 6.1, "smi timing values" updated t1.2 maximum to 300ns. rev. 2.1 (03-06-09) section 5.4.6 removed reference to internal por system. added note the nrst should be low until vddio and vdd_core are stable. added figure. ta b l e 5 . 3 4 corrected bit value for a symmetric and symmetric pause. section 6.3 improved timing values. section 5.4.8 enhanced this section. section 4.6.3 added information about register bit 18.14. section 6.6 added section on clock, wit h crystal specification table. figure 1.1 removed gpio from the led block. section 4.11 removed reference to gp01 pin in third paragraph. ta b l e 5 . 4 5 renamed bits 7-9 as reserved. ta b l e 5 . 2 8 renamed bits 7-9 as reserved. rev. 2.0 (07-15-08) chapter 9, package outline, tape and reel tape and reel drawings and ordering info added. rev. 1.9 (03-18-08) figure 6.7, "100m rmii transmit timing diagram" replaced figure. rev. 1.9 (03-18-08) table 6.5, "10m mii transmit timing values" removed the text ?t5.2? in the ?parameter? column. rev. 1.9 (03-18-08) figure 6.5, "10m mii transmit timing diagrams" replaced figure. rev. 1.9 (03-18-08) table 6.3, "100m mii transmit timing values" removed the text ?t3.2? in the ?parameter? column.
15kv esd protected mii/rmii 10/100 ethernet transceiver with hp auto-mdix support and flexpwr ? technology in a small footprint datasheet revision 2.3 (04-12-11) 82 smsc lan8700/lan8700i datasheet rev. 1.9 (03-18-08) figure 6.3, "100m mii transmit timing diagram" replaced figure. rev. 1.9 (03-18-08) table 6.11, "reset timing values" changed the min value for t11.3: from: ?400? to: ?10? rev. 1.9 (03-18-08) table 6.4, "10m m ii receive timing values" deleted last row in table. rev. 1.9 (03-18-08) section 4.6.2.1, "reference clock" first sentence of second paragraph changed: from: ?between 35% and 65%? to: ?between 40% and 60%? rev. 1.8 (02-14-08) ta b l e 6 . 7 changed value of t8.1 and t8.2. rev. 1.8 (02-14-08) ta b l e 6 . 6 changed value of t6.1. rev. 1.6 (12-11-07) section 4.9 added information about not applying vdd_core before vdd33 is at 2.64v. rev. 1.6 (12-11-07) table 3.8, "power signals" updated description of vdd_core for information on using external 1.8v supply. rev. 1.6 (12-11-07) table 3.1, "mii signals" updated description of rx_clk/regoff to add power supply sequencing information. rev. 1.6 (12-11-07) table 5.33, "register 3 - phy identifier 2" updated revision number to match the lan8700c silicon. rev. 1.5 (10-04-07) chapter 8, application notes figure 8.1 has been updated. in addition, the following cross reference added to caption: (see section 8.4, "reference designs" ). rev. 1.4 (09-17-07) section 7.1.4 changed vih to 0.68*vddio. changed vil to 0.4*vddio. rev. 1.3 (06-27-07) ta b l e 6 . 9 moved parameter t10.2 in ta b l e 6 . 9 from max column to min column. rev. 1.3 (06-27-07) ta b l e 6 . 5 moved parameter t5.2 in table 6.5 from max column to min column. rev. 1.2 (05-29-07) ta b l e 5 . 4 8 added description when the mode[2:0] bits are set to 110. rev. 1.2 (05-29-07) ta b l e 5 . 3 0 corrected default value for bit 0.11 to the value of 0. this bit does not get set when the mode[2:0] bits are set to 110. rev. 1.2 (05-23-07) section 5.4.9.2 added detail about mode[2:0] pins having no affect at soft reset. rev. 1.2 (05-23-07) ta b l e 5 . 3 0 added note to reset description (bit 0.15). rev. 1.2 (05-23-07) ta b l e 3 . 5 at nrst, added note that register bit values are loaded from the mode pins upon deassertion. table 10.1 customer revision history (continued) revision level & date section/figure/entry correction
15kv esd protected mii/rmii 10/100 ethernet transceiver with hp auto-mdix support and flexpwr ? technology in a small footprint datasheet smsc lan8700/lan8700i 83 revision 2.3 (04-12-11) datasheet rev. 1.2 (05-23-07) ta b l e 7 . 11 added rx_dv to table. rev. 1.2 (05-23-07) ta b l e 3 . 1 added note that rx_dv and rx_er cannot be high during reset. rev. 1.2 (05-23-07) ta b l e 6 . 7 moved parameter t8.2 from max column to min column. rev. 1.1 (04-17-07) ta b l e 7 . 4 changed column headings to add clarity regarding source of current. added note. rev. 1.1 (04-17-07) ta b l e 3 . 4 removed rx_clk/regoff because it made note 3.1 false. rev. 1.1 (04-12-07) ta b l e 5 . 4 0 added this table to describe the register. rev. 1.1 (04-12-07) ta b l e 5 . 2 9 added register 26. rev. 1.1 (04-12-07) ta b l e 5 . 2 3 changed description from reserved to symbol error counter. rev. 1.0 (04-04-07) table 5.30, ?register 0 - basic control,? on page 42 table modified: default column for ?power down? and ?isolate?. rev 1.0 (01-12-07) section 4.6.3, "mii vs. rmii configuration," on page 28 fixed a typo, gpo0/mii is on the 187, col/rmii/crs_dv is on the 8700. section 8.1, "app lication diagram," on page 75 added support components to crystal in application diagram circuit. also added a note to the bottom to indicate that purpose of r5 added. table 5.33, ?register 3 - phy identifier 2,? on page 43 corrected reg3 values. section 4.9.1, "disable the internal +1.8v regulator," on page 31 changed paragraph to correctly reflect operation vddio and vdda latch 1.8v regulator. 1.8v strap above vih or below vil. table 10.1 customer revision history (continued) revision level & date section/figure/entry correction

▲Up To Search▲

Price & Availability of LAN8700IC-AEZG

	To Download LAN8700IC-AEZG Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .